Revision 70

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trunk/librairies/polytech_ge/pont_diode/metadata/revision.dat
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		(Revision	0.0.2)
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......
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.2)
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						(Revision	0.0.3)
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						(ModificationStatus	NULL)
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......
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			)
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		)
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......
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......
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trunk/librairies/polytech_ge/pont_diode/sym_1/symbol.css
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L -75 125 -150 100 -1 16
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L -150 100 -100 50 -1 16
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L -100 50 -75 125 -1 16
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T 125 -25 0 0 47 0 0 0 0 1 82
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~
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T -125 -425 0 0 22 0 0 1 0 10 0
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PONT_DIODE
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P "PACK_TYPE" "GBPC-W" 150 -425 0 0 22 0 0 0 0 0 1 0 0
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P "$LOCATION" "?" -250 325 0 0 22 0 0 0 0 0 1 0 0
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P "PART_NAME" "PONT_DIODE" 0 0 0 0 22 0 0 0 0 0 0 0 0
......
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C -300 -350 "AC1" -322 -350 0 1 22 0 R
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L -300 0 -200 0 -1 0
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C -300 0 "AC" -322 0 0 1 22 0 R
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X "PIN_TEXT" "~" -150 -25 0 0 47 0 0 0 0 0 1 0 82
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trunk/librairies/polytech_ge/pont_diode/entity/pc.db
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-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 24, 2010  11:04:51
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-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 24, 2010  11:11:24
trunk/librairies/polytech_ge/pont_diode/entity/verilog.v
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// generated by newgenasym  Fri Sep 24 10:52:03 2010
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// generated by newgenasym  Fri Sep 24 11:11:24 2010
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module pont_diode (ac, ac1, \v+ , \v- );
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    input ac;
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    input ac1;
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    output \v+ ;
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    output \v- ;
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    inout ac;
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    inout ac1;
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    inout \v+ ;
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    inout \v- ;
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    initial
trunk/librairies/polytech_ge/pont_diode/entity/vhdl.vhd
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-- generated by newgenasym Fri Sep 24 10:52:03 2010
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-- generated by newgenasym Fri Sep 24 11:11:24 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity PONT_DIODE is
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entity pont_diode is
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    port (    
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	AC:        IN     STD_LOGIC;    
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	AC1:       IN     STD_LOGIC;    
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	\v+\:      OUT    STD_LOGIC;    
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	\v-\:      OUT    STD_LOGIC);
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end PONT_DIODE;
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	AC:        INOUT  STD_LOGIC;    
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	AC1:       INOUT  STD_LOGIC;    
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	\v+\:      INOUT  STD_LOGIC;    
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	\v-\:      INOUT  STD_LOGIC);
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end pont_diode;

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