Revision 67

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trunk/librairies/polytech_ge/pont_diode/sym_1/master.tag
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symbol.css
trunk/librairies/polytech_ge/pont_diode/sym_1/symbol.css
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C 300 -250 "V-" 325 -250 0 1 22 0 L
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C 300 250 "V+" 325 250 0 1 22 0 L
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C -300 -350 "AC1" -322 -350 0 1 22 0 R
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C -300 0 "AC" -322 0 0 1 22 0 R
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L -250 -400 -250 300 -1 0
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L -250 -400 250 -400 -1 0
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L -250 300 250 300 -1 0
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L 250 300 250 -400 -1 0
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L -300 -350 200 -350 -1 0
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L 200 -350 200 0 -1 16
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L 200 0 0 -200 -1 16
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L 200 0 0 200 -1 16
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L -200 0 0 200 -1 16
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L 0 200 0 250 -1 16
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L 0 -200 -200 0 -1 16
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L 0 -200 0 -250 -1 16
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L 300 -250 0 -250 -1 0
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L -300 0 -200 0 -1 0
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L 300 250 0 250 -1 0
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L 50 -100 100 -150 -1 16
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L -100 -150 -50 -100 -1 16
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L -100 150 -50 100 -1 16
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L 150 -100 75 -125 -1 16
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L 150 -100 100 -50 -1 16
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L 100 -50 75 -125 -1 16
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L -75 -125 -100 -50 -1 16
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L -150 -100 -75 -125 -1 16
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L -100 -50 -150 -100 -1 16
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L 75 125 100 50 -1 16
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L 100 50 150 100 -1 16
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L 150 100 75 125 -1 16
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L 50 100 100 150 -1 16
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L -75 125 -150 100 -1 16
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L -150 100 -100 50 -1 16
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L -100 50 -75 125 -1 16
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T -50 -250 0.00 0.00 47 0 0 0 0 1 82
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-
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T 125 -25 0.00 0.00 47 0 0 0 0 1 82
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~
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T -150 -25 0.00 0.00 47 0 0 0 0 1 82
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~
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T -75 200 0.00 0.00 47 0 0 0 0 1 82
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+
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T -125 -425 0.00 0.00 22 0 0 1 0 10 0
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PONT_DIODE
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P "PACK_TYPE" "thru" 150 -425 0.00 0.00 22 0 0 0 0 0 1 0 0
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P "$LOCATION" "?" -250 325 0.00 0.00 22 0 0 0 0 0 1 0 0
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P "PART_NAME" "PONT_DIODE" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "$PATH" "?" 25 25 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "CDS_LMAN_SYM_OUTLINE" "-250,150,250,-150" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
trunk/librairies/polytech_ge/pont_diode/entity/master.tag
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verilog.v
trunk/librairies/polytech_ge/pont_diode/entity/verilog.v
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// generated by newgenasym  Fri Sep 24 10:52:03 2010
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module pont_diode (ac, ac1, \v+ , \v- );
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    input ac;
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    input ac1;
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    output \v+ ;
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    output \v- ;
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    initial
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        begin
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        end
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endmodule
trunk/librairies/polytech_ge/pont_diode/entity/vhdl.vhd
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-- generated by newgenasym Fri Sep 24 10:52:03 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity PONT_DIODE is
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    port (    
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	AC:        IN     STD_LOGIC;    
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	AC1:       IN     STD_LOGIC;    
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	\v+\:      OUT    STD_LOGIC;    
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	\v-\:      OUT    STD_LOGIC);
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end PONT_DIODE;

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