Revision 59

View differences:

tags/0.5/librairies/polytech_ge_beta/vnh2sp30/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name PWM)
4
		(MSB )
5
		(LSB )
6
		(Type INPUT)
7
		(Location Left)
8
		(InputLoadLow -0.01)
9
		(InputLoadHigh 0.01)
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Both)
13
		(CheckIO Both)
14
		(CheckDir 1)
15
		(CheckAssert 1)
16
		(CheckOutput 1)
17
		(UnknownLoading 0)
18
		(PinShape )
19
	)
20

  
21
	(Pin
22
		(Name ENA/DIAGA)
23
		(MSB )
24
		(LSB )
25
		(Type BIDIR)
26
		(Location Left)
27
		(InputLoadLow -0.01)
28
		(InputLoadHigh 0.01)
29
		(OutputLoadLow 1.0)
30
		(OutputLoadHigh -1.0)
31
		(CheckLoad Both)
32
		(CheckIO Both)
33
		(CheckDir 1)
34
		(CheckAssert 1)
35
		(CheckOutput 1)
36
		(UnknownLoading 0)
37
		(PinShape )
38
	)
39

  
40
	(Pin
41
		(Name OUTA)
42
		(MSB 2)
43
		(LSB 0)
44
		(Type POWER)
45
		(Location Right)
46
		(InputLoadLow )
47
		(InputLoadHigh )
48
		(OutputLoadLow )
49
		(OutputLoadHigh )
50
		(CheckLoad Off)
51
		(CheckIO Off)
52
		(CheckDir 0)
53
		(CheckAssert 0)
54
		(CheckOutput 0)
55
		(UnknownLoading 0)
56
		(PinShape )
57
	)
58

  
59
	(Pin
60
		(Name GNDB)
61
		(MSB 2)
62
		(LSB 0)
63
		(Type GROUND)
64
		(Location Bottom)
65
		(InputLoadLow )
66
		(InputLoadHigh )
67
		(OutputLoadLow )
68
		(OutputLoadHigh )
69
		(CheckLoad Off)
70
		(CheckIO Off)
71
		(CheckDir 0)
72
		(CheckAssert 0)
73
		(CheckOutput 0)
74
		(UnknownLoading 0)
75
		(PinShape )
76
	)
77

  
78
	(Pin
79
		(Name INA)
80
		(MSB )
81
		(LSB )
82
		(Type INPUT)
83
		(Location Left)
84
		(InputLoadLow -0.01)
85
		(InputLoadHigh 0.01)
86
		(OutputLoadLow )
87
		(OutputLoadHigh )
88
		(CheckLoad Both)
89
		(CheckIO Both)
90
		(CheckDir 1)
91
		(CheckAssert 1)
92
		(CheckOutput 1)
93
		(UnknownLoading 0)
94
		(PinShape )
95
	)
96

  
97
	(Pin
98
		(Name INB)
99
		(MSB )
100
		(LSB )
101
		(Type INPUT)
102
		(Location Left)
103
		(InputLoadLow -0.01)
104
		(InputLoadHigh 0.01)
105
		(OutputLoadLow )
106
		(OutputLoadHigh )
107
		(CheckLoad Both)
108
		(CheckIO Both)
109
		(CheckDir 1)
110
		(CheckAssert 1)
111
		(CheckOutput 1)
112
		(UnknownLoading 0)
113
		(PinShape )
114
	)
115

  
116
	(Pin
117
		(Name OUTB)
118
		(MSB 2)
119
		(LSB 0)
120
		(Type POWER)
121
		(Location Right)
122
		(InputLoadLow )
123
		(InputLoadHigh )
124
		(OutputLoadLow )
125
		(OutputLoadHigh )
126
		(CheckLoad Off)
127
		(CheckIO Off)
128
		(CheckDir 0)
129
		(CheckAssert 0)
130
		(CheckOutput 0)
131
		(UnknownLoading 0)
132
		(PinShape )
133
	)
134

  
135
	(Pin
136
		(Name GNDA)
137
		(MSB 2)
138
		(LSB 0)
139
		(Type GROUND)
140
		(Location Bottom)
141
		(InputLoadLow )
142
		(InputLoadHigh )
143
		(OutputLoadLow )
144
		(OutputLoadHigh )
145
		(CheckLoad Off)
146
		(CheckIO Off)
147
		(CheckDir 0)
148
		(CheckAssert 0)
149
		(CheckOutput 0)
150
		(UnknownLoading 0)
151
		(PinShape )
152
	)
153

  
154
	(Pin
155
		(Name VCC)
156
		(MSB 2)
157
		(LSB 0)
158
		(Type POWER)
159
		(Location Top)
160
		(InputLoadLow )
161
		(InputLoadHigh )
162
		(OutputLoadLow )
163
		(OutputLoadHigh )
164
		(CheckLoad Off)
165
		(CheckIO Off)
166
		(CheckDir 0)
167
		(CheckAssert 0)
168
		(CheckOutput 0)
169
		(UnknownLoading 0)
170
		(PinShape )
171
	)
172

  
173
	(Pin
174
		(Name ENB/DIAGB)
175
		(MSB )
176
		(LSB )
177
		(Type BIDIR)
178
		(Location Left)
179
		(InputLoadLow -0.01)
180
		(InputLoadHigh 0.01)
181
		(OutputLoadLow 1.0)
182
		(OutputLoadHigh -1.0)
183
		(CheckLoad Both)
184
		(CheckIO Both)
185
		(CheckDir 1)
186
		(CheckAssert 1)
187
		(CheckOutput 1)
188
		(UnknownLoading 0)
189
		(PinShape )
190
	)
191

  
192

  
193
)
tags/0.5/librairies/polytech_ge_beta/vnh2sp30/metadata/master.tag
1
revision.dat
2
revision.log
3
revhistory.log
4
pinlist.txt
tags/0.5/librairies/polytech_ge_beta/vnh2sp30/metadata/revision.dat
1
(Cell	vnh2sp30
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3
	(RevisionInfoBlock	
4

  
5
		(Baselined	0)
6

  
7
		(Revision	0.0.1)
8

  
9
		(ModificationStatus	NULL)
10

  
11
		(Status	Created)
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13
		(ErrorStatus	0)
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15
		(CreateInfo	
16

  
17
			(Time	09/24/08,15:41:42)
18

  
19
			(User	ge)
20

  
21
			(Path	etudiants.vnh2sp30)
22

  
23
		)
24

  
25
	)
26

  
27
	(Views	
28

  
29
		(View	Symbol
30

  
31
			(Symbols	1
32

  
33
				(Symbol	sym_1
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35
					(Symbol_Type	Normal)
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					(Max_Size	0)
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					(Checksum	000000005546d4b4)
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.1)
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47
						(ModificationStatus	NULL)
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49
						(Status	Created)
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51
						(ErrorStatus	0)
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53
						(CreateInfo	
54

  
55
							(Time	09/24/08,15:41:42)
56

  
57
							(User	ge)
58

  
59
							(Path	etudiants.vnh2sp30)
60

  
61
						)
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					)
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				)
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			)
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			(Checksum	000000001b550383)
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		)
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73
		(View	Chips
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75
			(Checksum	00000000bd5b71c2)
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			(Primitives	1
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				(Primitive	vnh2sp30
80

  
81
					(RevisionInfoBlock	
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						(Baselined	0)
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85
						(Revision	0.0.1)
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87
						(ModificationStatus	NULL)
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89
						(Status	Created)
90

  
91
						(ErrorStatus	0)
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93
						(CreateInfo	
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							(Time	09/24/08,15:41:42)
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							(User	ge)
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							(Path	etudiants.vnh2sp30)
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101
						)
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					)
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					(LogicalPhysicalPartRelation	
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107
						(LogicalPart	vnh2sp30
108

  
109
							(PackType	vnh2sp30)
110

  
111
							(PackType	vnh2sp30_SMT)
112

  
113
						)
114

  
115
					)
116

  
117
					(Packages	2
118

  
119
						(FunctionGroups	1
120

  
121
							(FunctionGroup	1[1]
122

  
123
								(Linkages	
124

  
125
									(Linkage	Symbol
126

  
127
										(Name	sym_1)
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									)
130

  
131
								)
132

  
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							)
134

  
135
						)
136

  
137
						(Linkages	
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139
							(DefaultFootPrint	
140

  
141
								(Name	MPSO30)
142

  
143
							)
144

  
145
						)
146

  
147
					)
148

  
149
				)
150

  
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			)
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		)
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		(Checksum	000000001ccc0384)
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	)
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	(VersionInfoBlock	
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		(ToolName	PDV)
162

  
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		(Version	16.0-p002 (v16-0-87B))
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		(License	PCB_design_expert)
166

  
167
	)
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169
	(Checksum	000000001d4b03aa)
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)
172

  
tags/0.5/librairies/polytech_ge_beta/vnh2sp30/chips/master.tag
1
chips.prt
tags/0.5/librairies/polytech_ge_beta/vnh2sp30/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'VNH2SP30','VNH2SP30_SMT';
3
  pin
4
    'INA':
5
      PIN_NUMBER='(5)';
6
      INPUT_LOAD='(-0.01,0.01)';
7
    'INB':
8
      PIN_NUMBER='(11)';
9
      INPUT_LOAD='(-0.01,0.01)';
10
    'ENA/DIAGA':
11
      PIN_NUMBER='(6)';
12
      BIDIRECTIONAL='TRUE';
13
      INPUT_LOAD='(-0.01,0.01)';
14
      OUTPUT_LOAD='(1.0,-1.0)';
15
    'ENB/DIAGB':
16
      PIN_NUMBER='(10)';
17
      BIDIRECTIONAL='TRUE';
18
      INPUT_LOAD='(-0.01,0.01)';
19
      OUTPUT_LOAD='(1.0,-1.0)';
20
    'PWM':
21
      PIN_NUMBER='(8)';
22
      INPUT_LOAD='(-0.01,0.01)';
23
    'OUTA'<0>:
24
      PIN_NUMBER='(1)';
25
      PINUSE='POWER';
26
    'OUTA'<1>:
27
      PIN_NUMBER='(25)';
28
      PINUSE='POWER';
29
    'OUTA'<2>:
30
      PIN_NUMBER='(30)';
31
      PINUSE='POWER';
32
    'OUTB'<0>:
33
      PIN_NUMBER='(15)';
34
      PINUSE='POWER';
35
    'OUTB'<1>:
36
      PIN_NUMBER='(16)';
37
      PINUSE='POWER';
38
    'OUTB'<2>:
39
      PIN_NUMBER='(21)';
40
      PINUSE='POWER';
41
    'VCC'<0>:
42
      PIN_NUMBER='(3)';
43
      PINUSE='POWER';
44
    'VCC'<1>:
45
      PIN_NUMBER='(13)';
46
      PINUSE='POWER';
47
    'VCC'<2>:
48
      PIN_NUMBER='(23)';
49
      PINUSE='POWER';
50
    'GNDA'<0>:
51
      PIN_NUMBER='(26)';
52
      PINUSE='GROUND';
53
    'GNDA'<1>:
54
      PIN_NUMBER='(27)';
55
      PINUSE='GROUND';
56
    'GNDA'<2>:
57
      PIN_NUMBER='(28)';
58
      PINUSE='GROUND';
59
    'GNDB'<0>:
60
      PIN_NUMBER='(20)';
61
      PINUSE='GROUND';
62
    'GNDB'<1>:
63
      PIN_NUMBER='(18)';
64
      PINUSE='GROUND';
65
    'GNDB'<2>:
66
      PIN_NUMBER='(19)';
67
      PINUSE='GROUND';
68
  end_pin;
69
  body
70
    PART_NAME='vnh2sp30';
71
    BODY_NAME='VNH2SP30';
72
    JEDEC_TYPE='MPSO30';
73
    PHYS_DES_PREFIX='U';
74
    CLASS='IC';
75
    NC_PINS='(2,4,7,9,12,14,17,22,24,29)';
76
  end_body;
77
end_primitive;
78

  
79
END.
tags/0.5/librairies/polytech_ge_beta/vnh2sp30/sym_1/master.tag
1
symbol.css
tags/0.5/librairies/polytech_ge_beta/vnh2sp30/sym_1/symbol.css
1
P "CDS_LMAN_SYM_OUTLINE" "-350,300,150,-300" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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L -350 -300 -350 300 -1 0
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L 150 300 -350 300 -1 0
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L -350 -300 150 -300 -1 0
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L 150 300 150 -300 -1 0
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T -150 -200 0 0 22 0 0 1 0 8 0
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VNH3SP30
8
P "LOCATION" "U?" -400 400 0 0 22 0 0 0 0 0 1 0 0
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P "$PATH" "?" 25 25 0 0 22 0 0 0 0 0 0 0 0
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0 0 22 0 0 0 0 0 0 0 0
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P "PART_NAME" "vnh2sp30" 25 125 0 0 22 0 0 0 0 0 0 0 0
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P "PACK_TYPE" "SMT" 25 125 0 0 22 0 0 0 0 0 0 0 0
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L -400 50 -350 50 -1 0
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C -400 50 "PWM" -422 50 0 1 22 0 R
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X "PIN_TEXT" "PWM" -325 50 0 0 22 0 0 0 0 0 1 0 0
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L -400 -50 -350 -50 -1 0
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C -400 -50 "ENA/DIAGA" -422 -50 0 1 22 0 R
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X "PIN_TEXT" "ENA/DIAGA" -325 -50 0 0 22 0 0 0 0 0 1 0 0
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L 200 150 150 150 -1 0
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C 200 150 "OUTA<1>" 222 150 0 1 22 0 L
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L 200 200 150 200 -1 0
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C 200 200 "OUTA<0>" 222 200 0 1 22 0 L
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X "PIN_TEXT" "OUTA<0>" 125 200 0 0 22 0 0 2 0 0 1 0 0
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L -300 -350 -300 -300 -1 0
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C -300 -350 "GNDB<0>" -300 -372 0 1 22 1 R
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X "PIN_TEXT" "GNDB" -300 -275 0 0 22 0 0 0 0 0 1 0 0
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L -400 200 -350 200 -1 0
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C -400 200 "INA" -422 200 0 1 22 0 R
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X "PIN_TEXT" "INA" -325 200 0 0 22 0 0 0 0 0 1 0 0
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L -400 150 -350 150 -1 0
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C -400 150 "INB" -422 150 0 1 22 0 R
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X "PIN_TEXT" "INB" -325 150 0 0 22 0 0 0 0 0 1 0 0
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L 200 100 150 100 -1 0
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C 200 100 "OUTA<2>" 222 100 0 1 22 0 L
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X "PIN_TEXT" "OUTA<2>" 125 100 0 0 22 0 0 2 0 0 1 0 0
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L 200 -50 150 -50 -1 0
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C 200 -50 "OUTB<0>" 222 -50 0 1 22 0 L
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L 200 -100 150 -100 -1 0
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C 200 -100 "OUTB<1>" 222 -100 0 1 22 0 L
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X "PIN_TEXT" "OUTB<1>" 125 -100 0 0 22 0 0 2 0 0 1 0 0
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L 200 -150 150 -150 -1 0
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C 200 -150 "OUTB<2>" 222 -150 0 1 22 0 L
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X "PIN_TEXT" "OUTB<2>" 125 -150 0 0 22 0 0 2 0 0 1 0 0
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C -250 -350 "GNDB<1>" -250 -372 0 1 22 1 R
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L -200 -350 -200 -300 -1 0
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C -200 -350 "GNDB<2>" -200 -372 0 1 22 1 R
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L -50 -350 -50 -300 -1 0
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C -50 -350 "GNDA<0>" -50 -372 0 1 22 1 R
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X "PIN_TEXT" "GNDA" -50 -275 0 0 22 0 0 0 0 0 1 0 0
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C 50 -350 "GNDA<2>" 50 -372 0 1 22 1 R
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L 0 -350 0 -300 -1 0
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C 0 -350 "GNDA<1>" 0 -372 0 1 22 1 R
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L -200 350 -200 300 -1 0
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C -200 350 "VCC<0>" -200 372 0 1 22 1 L
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X "PIN_TEXT" "VCC" -100 250 0 0 22 0 0 2 0 0 1 0 0
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L -150 350 -150 300 -1 0
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C -150 350 "VCC<1>" -150 372 0 1 22 1 L
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L -100 350 -100 300 -1 0
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C -100 350 "VCC<2>" -100 372 0 1 22 1 L
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L -400 -100 -350 -100 -1 0
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C -400 -100 "ENB/DIAGB" -422 -100 0 1 22 0 R
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68

  
tags/0.5/librairies/polytech_ge_beta/vnh2sp30/entity/master.tag
1
vhdl.vhd
2
verilog.v
tags/0.5/librairies/polytech_ge_beta/vnh2sp30/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 24, 2008  15:41:42
tags/0.5/librairies/polytech_ge_beta/vnh2sp30/entity/verilog.v
1
// generated by newgenasym  Wed Sep 24 15:41:42 2008
2

  
3

  
4
module vnh2sp30 (\ena/diaga , \enb/diagb , gnda, gndb, ina, inb, outa, outb, pwm,
5
        vcc);
6
    inout \ena/diaga ;
7
    inout \enb/diagb ;
8
    input [2:0] gnda;
9
    input [2:0] gndb;
10
    input ina;
11
    input inb;
12
    input [2:0] outa;
13
    input [2:0] outb;
14
    input pwm;
15
    input [2:0] vcc;
16

  
17

  
18
    initial
19
        begin
20
        end
21

  
22
endmodule
tags/0.5/librairies/polytech_ge_beta/vnh2sp30/entity/vhdl.vhd
1
-- generated by newgenasym Wed Sep 24 15:41:42 2008
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity vnh2sp30 is
7
    port (    
8
	\ena/diaga\: INOUT  STD_LOGIC;    
9
	\enb/diagb\: INOUT  STD_LOGIC;    
10
	GNDA:      IN     STD_LOGIC_VECTOR (2 DOWNTO 0);    
11
	GNDB:      IN     STD_LOGIC_VECTOR (2 DOWNTO 0);    
12
	INA:       IN     STD_LOGIC;    
13
	INB:       IN     STD_LOGIC;    
14
	OUTA:      IN     STD_LOGIC_VECTOR (2 DOWNTO 0);    
15
	OUTB:      IN     STD_LOGIC_VECTOR (2 DOWNTO 0);    
16
	PWM:       IN     STD_LOGIC;    
17
	VCC:       IN     STD_LOGIC_VECTOR (2 DOWNTO 0));
18
end vnh2sp30;
tags/0.5/librairies/polytech_ge_beta/adis16364/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name DIO3)
4
		(MSB )
5
		(LSB )
6
		(Type ANALOG)
7
		(Location Left)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name DIO4/CLKIN)
25
		(MSB )
26
		(LSB )
27
		(Type ANALOG)
28
		(Location Left)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow )
32
		(OutputLoadHigh )
33
		(CheckLoad Off)
34
		(CheckIO Off)
35
		(CheckDir 0)
36
		(CheckAssert 0)
37
		(CheckOutput 0)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name SCLK)
46
		(MSB )
47
		(LSB )
48
		(Type ANALOG)
49
		(Location Left)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow )
53
		(OutputLoadHigh )
54
		(CheckLoad Off)
55
		(CheckIO Off)
56
		(CheckDir 0)
57
		(CheckAssert 0)
58
		(CheckOutput 0)
59
		(UnknownLoading 0)
60
		(PinShape Line)
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name DOUT)
67
		(MSB )
68
		(LSB )
69
		(Type ANALOG)
70
		(Location Left)
71
		(InputLoadLow )
72
		(InputLoadHigh )
73
		(OutputLoadLow )
74
		(OutputLoadHigh )
75
		(CheckLoad Off)
76
		(CheckIO Off)
77
		(CheckDir 0)
78
		(CheckAssert 0)
79
		(CheckOutput 0)
80
		(UnknownLoading 0)
81
		(PinShape Line)
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name DIN)
88
		(MSB )
89
		(LSB )
90
		(Type ANALOG)
91
		(Location Left)
92
		(InputLoadLow )
93
		(InputLoadHigh )
94
		(OutputLoadLow )
95
		(OutputLoadHigh )
96
		(CheckLoad Off)
97
		(CheckIO Off)
98
		(CheckDir 0)
99
		(CheckAssert 0)
100
		(CheckOutput 0)
101
		(UnknownLoading 0)
102
		(PinShape Line)
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name /CS)
109
		(MSB )
110
		(LSB )
111
		(Type ANALOG)
112
		(Location Left)
113
		(InputLoadLow )
114
		(InputLoadHigh )
115
		(OutputLoadLow )
116
		(OutputLoadHigh )
117
		(CheckLoad Off)
118
		(CheckIO Off)
119
		(CheckDir 0)
120
		(CheckAssert 0)
121
		(CheckOutput 0)
122
		(UnknownLoading 0)
123
		(PinShape Line)
124
		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
126
	)
127

  
128
	(Pin
129
		(Name DIO1)
130
		(MSB )
131
		(LSB )
132
		(Type ANALOG)
133
		(Location Left)
134
		(InputLoadLow )
135
		(InputLoadHigh )
136
		(OutputLoadLow )
137
		(OutputLoadHigh )
138
		(CheckLoad Off)
139
		(CheckIO Off)
140
		(CheckDir 0)
141
		(CheckAssert 0)
142
		(CheckOutput 0)
143
		(UnknownLoading 0)
144
		(PinShape Line)
145
		(DIFF_PAIR_PINS_POS )
146
		(DIFF_PAIR_PINS_NEG )
147
	)
148

  
149
	(Pin
150
		(Name /RST)
151
		(MSB )
152
		(LSB )
153
		(Type ANALOG)
154
		(Location Left)
155
		(InputLoadLow )
156
		(InputLoadHigh )
157
		(OutputLoadLow )
158
		(OutputLoadHigh )
159
		(CheckLoad Off)
160
		(CheckIO Off)
161
		(CheckDir 0)
162
		(CheckAssert 0)
163
		(CheckOutput 0)
164
		(UnknownLoading 0)
165
		(PinShape Line)
166
		(DIFF_PAIR_PINS_POS )
167
		(DIFF_PAIR_PINS_NEG )
168
	)
169

  
170
	(Pin
171
		(Name DIO2)
172
		(MSB )
173
		(LSB )
174
		(Type ANALOG)
175
		(Location Left)
176
		(InputLoadLow )
177
		(InputLoadHigh )
178
		(OutputLoadLow )
179
		(OutputLoadHigh )
180
		(CheckLoad Off)
181
		(CheckIO Off)
182
		(CheckDir 0)
183
		(CheckAssert 0)
184
		(CheckOutput 0)
185
		(UnknownLoading 0)
186
		(PinShape Line)
187
		(DIFF_PAIR_PINS_POS )
188
		(DIFF_PAIR_PINS_NEG )
189
	)
190

  
191
	(Pin
192
		(Name AUX_DAC)
193
		(MSB )
194
		(LSB )
195
		(Type ANALOG)
196
		(Location Left)
197
		(InputLoadLow )
198
		(InputLoadHigh )
199
		(OutputLoadLow )
200
		(OutputLoadHigh )
201
		(CheckLoad Off)
202
		(CheckIO Off)
203
		(CheckDir 0)
204
		(CheckAssert 0)
205
		(CheckOutput 0)
206
		(UnknownLoading 0)
207
		(PinShape Line)
208
		(DIFF_PAIR_PINS_POS )
209
		(DIFF_PAIR_PINS_NEG )
210
	)
211

  
212
	(Pin
213
		(Name AUX_ADC)
214
		(MSB )
215
		(LSB )
216
		(Type ANALOG)
217
		(Location Left)
218
		(InputLoadLow )
219
		(InputLoadHigh )
220
		(OutputLoadLow )
221
		(OutputLoadHigh )
222
		(CheckLoad Off)
223
		(CheckIO Off)
224
		(CheckDir 0)
225
		(CheckAssert 0)
226
		(CheckOutput 0)
227
		(UnknownLoading 0)
228
		(PinShape Line)
229
		(DIFF_PAIR_PINS_POS )
230
		(DIFF_PAIR_PINS_NEG )
231
	)
232

  
233
	(Pin
234
		(Name VCC)
235
		(MSB 2)
236
		(LSB 0)
237
		(Type POWER)
238
		(Location Top)
239
		(InputLoadLow )
240
		(InputLoadHigh )
241
		(OutputLoadLow )
242
		(OutputLoadHigh )
243
		(CheckLoad Off)
244
		(CheckIO Off)
245
		(CheckDir 0)
246
		(CheckAssert 0)
247
		(CheckOutput 0)
248
		(UnknownLoading 0)
249
		(PinShape Line)
250
		(DIFF_PAIR_PINS_POS )
251
		(DIFF_PAIR_PINS_NEG )
252
	)
253

  
254
	(Pin
255
		(Name GND)
256
		(MSB 2)
257
		(LSB 0)
258
		(Type GROUND)
259
		(Location Top)
260
		(InputLoadLow )
261
		(InputLoadHigh )
262
		(OutputLoadLow )
263
		(OutputLoadHigh )
264
		(CheckLoad Off)
265
		(CheckIO Off)
266
		(CheckDir 0)
267
		(CheckAssert 0)
268
		(CheckOutput 0)
269
		(UnknownLoading 0)
270
		(PinShape Line)
271
		(DIFF_PAIR_PINS_POS )
272
		(DIFF_PAIR_PINS_NEG )
273
	)
274

  
275

  
276
)
tags/0.5/librairies/polytech_ge_beta/adis16364/metadata/master.tag
1
revision.dat
tags/0.5/librairies/polytech_ge_beta/adis16364/metadata/revision.dat
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tags/0.5/librairies/polytech_ge_beta/adis16364/chips/master.tag
1
chips.prt
tags/0.5/librairies/polytech_ge_beta/adis16364/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'ADIS16364';
3
  pin
4
    'DIO3':
5
      PIN_NUMBER='(1)';
6
      PIN_TYPE='ANALOG';
7
      NO_LOAD_CHECK='Both';
8
      NO_IO_CHECK='Both';
9
      NO_ASSERT_CHECK='TRUE';
10
      NO_DIR_CHECK='TRUE';
11
      ALLOW_CONNECT='TRUE';
12
    'DIO4/CLKIN':
13
      PIN_NUMBER='(2)';
14
      PIN_TYPE='ANALOG';
15
      NO_LOAD_CHECK='Both';
16
      NO_IO_CHECK='Both';
17
      NO_ASSERT_CHECK='TRUE';
18
      NO_DIR_CHECK='TRUE';
19
      ALLOW_CONNECT='TRUE';
20
    'SCLK':
21
      PIN_NUMBER='(3)';
22
      PIN_TYPE='ANALOG';
23
      NO_LOAD_CHECK='Both';
24
      NO_IO_CHECK='Both';
25
      NO_ASSERT_CHECK='TRUE';
26
      NO_DIR_CHECK='TRUE';
27
      ALLOW_CONNECT='TRUE';
28
    'DOUT':
29
      PIN_NUMBER='(4)';
30
      PIN_TYPE='ANALOG';
31
      NO_LOAD_CHECK='Both';
32
      NO_IO_CHECK='Both';
33
      NO_ASSERT_CHECK='TRUE';
34
      NO_DIR_CHECK='TRUE';
35
      ALLOW_CONNECT='TRUE';
36
    'DIN':
37
      PIN_NUMBER='(5)';
38
      PIN_TYPE='ANALOG';
39
      NO_LOAD_CHECK='Both';
40
      NO_IO_CHECK='Both';
41
      NO_ASSERT_CHECK='TRUE';
42
      NO_DIR_CHECK='TRUE';
43
      ALLOW_CONNECT='TRUE';
44
    '/CS':
45
      PIN_NUMBER='(6)';
46
      PIN_TYPE='ANALOG';
47
      NO_LOAD_CHECK='Both';
48
      NO_IO_CHECK='Both';
49
      NO_ASSERT_CHECK='TRUE';
50
      NO_DIR_CHECK='TRUE';
51
      ALLOW_CONNECT='TRUE';
52
    'DIO1':
53
      PIN_NUMBER='(7)';
54
      PIN_TYPE='ANALOG';
55
      NO_LOAD_CHECK='Both';
56
      NO_IO_CHECK='Both';
57
      NO_ASSERT_CHECK='TRUE';
58
      NO_DIR_CHECK='TRUE';
59
      ALLOW_CONNECT='TRUE';
60
    '/RST':
61
      PIN_NUMBER='(8)';
62
      PIN_TYPE='ANALOG';
63
      NO_LOAD_CHECK='Both';
64
      NO_IO_CHECK='Both';
65
      NO_ASSERT_CHECK='TRUE';
66
      NO_DIR_CHECK='TRUE';
67
      ALLOW_CONNECT='TRUE';
68
    'DIO2':
69
      PIN_NUMBER='(9)';
70
      PIN_TYPE='ANALOG';
71
      NO_LOAD_CHECK='Both';
72
      NO_IO_CHECK='Both';
73
      NO_ASSERT_CHECK='TRUE';
74
      NO_DIR_CHECK='TRUE';
75
      ALLOW_CONNECT='TRUE';
76
    'AUX_DAC':
77
      PIN_NUMBER='(20)';
78
      PIN_TYPE='ANALOG';
79
      NO_LOAD_CHECK='Both';
80
      NO_IO_CHECK='Both';
81
      NO_ASSERT_CHECK='TRUE';
82
      NO_DIR_CHECK='TRUE';
83
      ALLOW_CONNECT='TRUE';
84
    'AUX_ADC':
85
      PIN_NUMBER='(21)';
86
      PIN_TYPE='ANALOG';
87
      NO_LOAD_CHECK='Both';
88
      NO_IO_CHECK='Both';
89
      NO_ASSERT_CHECK='TRUE';
90
      NO_DIR_CHECK='TRUE';
91
      ALLOW_CONNECT='TRUE';
92
    'VCC'<0>:
93
      PIN_NUMBER='(10)';
94
      PINUSE='POWER';
95
      NO_LOAD_CHECK='Both';
96
      NO_IO_CHECK='Both';
97
      NO_ASSERT_CHECK='TRUE';
98
      NO_DIR_CHECK='TRUE';
99
      ALLOW_CONNECT='TRUE';
100
    'VCC'<1>:
101
      PIN_NUMBER='(11)';
102
      PINUSE='POWER';
103
      NO_LOAD_CHECK='Both';
104
      NO_IO_CHECK='Both';
105
      NO_ASSERT_CHECK='TRUE';
106
      NO_DIR_CHECK='TRUE';
107
      ALLOW_CONNECT='TRUE';
108
    'VCC'<2>:
109
      PIN_NUMBER='(12)';
110
      PINUSE='POWER';
111
      NO_LOAD_CHECK='Both';
112
      NO_IO_CHECK='Both';
113
      NO_ASSERT_CHECK='TRUE';
114
      NO_DIR_CHECK='TRUE';
115
      ALLOW_CONNECT='TRUE';
116
    'GND'<0>:
117
      PIN_NUMBER='(13)';
118
      PINUSE='GROUND';
119
      NO_LOAD_CHECK='Both';
120
      NO_IO_CHECK='Both';
121
      NO_ASSERT_CHECK='TRUE';
122
      NO_DIR_CHECK='TRUE';
123
      ALLOW_CONNECT='TRUE';
124
    'GND'<1>:
125
      PIN_NUMBER='(14)';
126
      PINUSE='GROUND';
127
      NO_LOAD_CHECK='Both';
128
      NO_IO_CHECK='Both';
129
      NO_ASSERT_CHECK='TRUE';
130
      NO_DIR_CHECK='TRUE';
131
      ALLOW_CONNECT='TRUE';
132
    'GND'<2>:
133
      PIN_NUMBER='(15)';
134
      PINUSE='GROUND';
135
      NO_LOAD_CHECK='Both';
136
      NO_IO_CHECK='Both';
137
      NO_ASSERT_CHECK='TRUE';
138
      NO_DIR_CHECK='TRUE';
139
      ALLOW_CONNECT='TRUE';
140
  end_pin;
141
  body
142
    PART_NAME='ADIS16364';
143
    BODY_NAME='ADIS16364';
144
    JEDEC_TYPE='adis16364';
145
    PHYS_DES_PREFIX='U';
146
    CLASS='IC';
147
    NC_PINS='(16,17,18,19,22,23,24)';
148
  end_body;
149
end_primitive;
150

  
151
END.
tags/0.5/librairies/polytech_ge_beta/adis16364/sym_1/master.tag
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symbol.css
tags/0.5/librairies/polytech_ge_beta/adis16364/sym_1/symbol.css
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L -125 325 350 325 -1 0
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L 350 325 350 -775 -1 0
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L -125 -775 350 -775 -1 0
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T 126 250 0 0 29 0 0 1 0 9 0
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adis16364
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L 400 150 350 150 -1 0
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C 400 150 "DIO3" 425 150 0 1 29 0 L
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X "PIN_TEXT" "DIO3" 340 150 0 0 23 0 0 2 0 0 1 0 0
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L -175 150 -125 150 -1 0
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C -175 150 "DIO4/CLKIN" -200 150 0 1 29 0 R
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C -175 50 "DOUT" -200 50 0 1 29 0 R
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X "PIN_TEXT" "DOUT" -115 50 0 0 23 0 0 0 0 0 1 0 0
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L 400 -50 350 -50 -1 0
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C 400 -50 "DIN" 425 -50 0 1 29 0 L
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X "PIN_TEXT" "DIN" 340 -50 0 0 23 0 0 2 0 0 1 0 0
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L -175 -50 -125 -50 -1 0
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L 400 -150 350 -150 -1 0
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L -175 -150 -125 -150 -1 0
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C -175 -150 "/RST" -200 -150 0 1 29 0 R
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C 400 -250 "DIO2" 425 -250 0 1 29 0 L
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L -175 -600 -125 -600 -1 0
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C -175 -600 "AUX_DAC" -200 -600 0 1 29 0 R
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L -175 -250 -125 -250 -1 0
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C -175 -250 "VCC<0>" -200 -250 0 1 29 0 R
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X "PIN_TEXT" "VCC[0]" -115 -250 0 0 23 0 0 0 0 0 1 0 0
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C 400 -350 "VCC<1>" 425 -350 0 1 29 0 L
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L -175 -350 -125 -350 -1 0
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C -175 -350 "VCC<2>" -200 -350 0 1 29 0 R
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X "PIN_TEXT" "VCC[2]" -115 -350 0 0 23 0 0 0 0 0 1 0 0
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L -175 -500 -125 -500 -1 0
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C -175 -500 "GND<0>" -200 -500 0 1 29 0 R
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X "PIN_TEXT" "GND[0]" -115 -500 0 0 23 0 0 0 0 0 1 0 0
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L 400 -500 350 -500 -1 0
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C 400 -500 "GND<1>" 425 -500 0 1 29 0 L
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X "PIN_TEXT" "GND[1]" 340 -500 0 0 23 0 0 2 0 0 1 0 0
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L 400 -600 350 -600 -1 0
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C 400 -600 "GND<2>" 425 -600 0 1 29 0 L
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tags/0.5/librairies/polytech_ge_beta/adis16364/entity/master.tag
1
verilog.v
tags/0.5/librairies/polytech_ge_beta/adis16364/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct  7, 2009  15:14:16
tags/0.5/librairies/polytech_ge_beta/adis16364/entity/verilog.v
1
// generated by newgenasym  Wed Oct 07 15:14:16 2009
2

  
3

  
4
module adis16364 (\/cs , \/rst , aux_adc, aux_dac, din, dio1, dio2, dio3,
5
        \dio4/clkin , dout, gnd, sclk, vcc);
6
    inout \/cs ;
7
    inout \/rst ;
8
    inout aux_adc;
9
    inout aux_dac;
10
    inout din;
11
    inout dio1;
12
    inout dio2;
13
    inout dio3;
14
    inout \dio4/clkin ;
15
    inout dout;
16
    input [2:0] gnd;
17
    inout sclk;
18
    input [2:0] vcc;
19

  
20

  
21
    initial
22
        begin
23
        end
24

  
25
endmodule
tags/0.5/librairies/polytech_ge_beta/adis16364/entity/vhdl.vhd
1
-- generated by newgenasym Wed Oct 07 15:14:16 2009
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity adis16364 is
7
    port (    
8
	\/cs\:     INOUT  STD_LOGIC;    
9
	\/rst\:    INOUT  STD_LOGIC;    
10
	AUX_ADC:   INOUT  STD_LOGIC;    
11
	AUX_DAC:   INOUT  STD_LOGIC;    
12
	DIN:       INOUT  STD_LOGIC;    
13
	DIO1:      INOUT  STD_LOGIC;    
14
	DIO2:      INOUT  STD_LOGIC;    
15
	DIO3:      INOUT  STD_LOGIC;    
16
	\dio4/clkin\: INOUT  STD_LOGIC;    
17
	DOUT:      INOUT  STD_LOGIC;    
18
	GND:       IN     STD_LOGIC_VECTOR (2 DOWNTO 0);    
19
	SCLK:      INOUT  STD_LOGIC;    
20
	VCC:       IN     STD_LOGIC_VECTOR (2 DOWNTO 0));
21
end adis16364;
tags/0.5/librairies/polytech_ge_beta/rj45/cfg_analog/master.tag
1
expand.cfg
tags/0.5/librairies/polytech_ge_beta/rj45/cfg_analog/expand.cfg
1
config rj45;
2
design james.rj45:sch_1;
3
liblist voiture_lib, james, laffont, standard, cust, opamp;
4
viewlist awb_dev, vhdla, vloga, spectrehdl, spice_1, sch_1, entity;
5
stoplist awb_dev, vhdla, vloga, spectrehdl;
6
endconfig
tags/0.5/librairies/polytech_ge_beta/rj45/chips/master.tag
1
chips.prt
tags/0.5/librairies/polytech_ge_beta/rj45/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
TIME=' Created/Modified on Wed Sep 22 20:32:22 2004' ;
3
primitive 'RJ45','RJ45_THRU';
4
  pin
5
    'P1':
6
      PIN_NUMBER='(1)';
7
      INPUT_LOAD='(-0.01,0.01)';
8
      OUTPUT_LOAD='(1.0,-1.0)';
9
      BIDIRECTIONAL='TRUE';
10
    'P2':
11
      PIN_NUMBER='(2)';
12
      INPUT_LOAD='(-0.01,0.01)';
13
      OUTPUT_LOAD='(1.0,-1.0)';
14
      BIDIRECTIONAL='TRUE';
15
    'P3':
16
      PIN_NUMBER='(3)';
17
      INPUT_LOAD='(-0.01,0.01)';
18
      OUTPUT_LOAD='(1.0,-1.0)';
19
      BIDIRECTIONAL='TRUE';
20
    'P4':
21
      PIN_NUMBER='(4)';
22
      INPUT_LOAD='(-0.01,0.01)';
23
      OUTPUT_LOAD='(1.0,-1.0)';
24
      BIDIRECTIONAL='TRUE';
25
    'P5':
26
      PIN_NUMBER='(5)';
27
      INPUT_LOAD='(-0.01,0.01)';
28
      OUTPUT_LOAD='(1.0,-1.0)';
29
      BIDIRECTIONAL='TRUE';
30
    'P6':
31
      PIN_NUMBER='(6)';
32
      INPUT_LOAD='(-0.01,0.01)';
33
      OUTPUT_LOAD='(1.0,-1.0)';
34
      BIDIRECTIONAL='TRUE';
35
    'P7':
36
      PIN_NUMBER='(7)';
37
      INPUT_LOAD='(-0.01,0.01)';
38
      OUTPUT_LOAD='(1.0,-1.0)';
39
      BIDIRECTIONAL='TRUE';
40
    'P8':
41
      PIN_NUMBER='(8)';
42
      INPUT_LOAD='(-0.01,0.01)';
43
      OUTPUT_LOAD='(1.0,-1.0)';
44
      BIDIRECTIONAL='TRUE';
45
  end_pin;
46
  body
47
    NC_PINS='(9,10)';
48
    CLASS='IO';
49
    PART_NAME='RJ45';
50
    PHYS_DES_PREFIX='J';
51
    JEDEC_TYPE='rj45';
52
  end_body;
53
end_primitive;
54
END.
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