Revision 58

View differences:

tags/0.5/librairies/polytech_ge/vcc_5v/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name VCC_BAR)
4
		(MSB )
5
		(LSB )
6
		(Type UNSPEC)
7
		(Location Bottom)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23

  
24
)
tags/0.5/librairies/polytech_ge/vcc_5v/metadata/master.tag
1
revision.dat
tags/0.5/librairies/polytech_ge/vcc_5v/metadata/revision.dat
1
(Cell	Vcc_5v
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3
	(RevisionInfoBlock	
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		(Revision	0.0.4)
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		(ModificationStatus	NULL)
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11
		(Status	Created)
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13
		(ErrorStatus	0)
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15
		(CreateInfo	
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17
			(Time	10/21/09,14:09:58)
18

  
19
			(User	tchillet)
20

  
21
			(Path	ge.Vcc_5v)
22

  
23
		)
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25
	)
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27
	(Views	
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		(View	Symbol
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			(Symbols	1
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33
				(Symbol	sym_1
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					(Symbol_Type	Normal)
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					(Max_Size	0)
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					(Checksum	000000006c9e3338)
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.4)
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47
						(ModificationStatus	NULL)
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49
						(Status	Created)
50

  
51
						(ErrorStatus	0)
52

  
53
						(CreateInfo	
54

  
55
							(Time	10/21/09,14:09:58)
56

  
57
							(User	tchillet)
58

  
59
							(Path	ge.Vcc_5v)
60

  
61
						)
62

  
63
					)
64

  
65
				)
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67
			)
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			(Checksum	000000001c870389)
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		(Checksum	000000001b720358)
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	)
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	(VersionInfoBlock	
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		(ToolName	PDV)
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		(Version	16.01-s021 (v16-1-53AR))
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		(License	PCB_librarian_expert)
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	)
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	(Checksum	000000001b45034d)
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)
90

  
tags/0.5/librairies/polytech_ge/vcc_5v/sym_1/master.tag
1
symbol.css
tags/0.5/librairies/polytech_ge/vcc_5v/sym_1/symbol.css
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P "CDS_LMAN_SYM_OUTLINE" "-125,125,125,-125" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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L 25 0 -25 0 -1 0
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P "HDL_POWER" "Vcc_5v" -125 25 0 0 41 0 0 0 0 0 1 0 32
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P "BODY_TYPE" "PLUMBING" -45 -43 0 0 16 0 0 0 0 0 0 0 0
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L 0 0 0 -50 -1 0
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C 0 -50 "VCC_BAR" 5 -65 0 1 15 0 L
7

  
8

  
tags/0.5/librairies/polytech_ge/2n2222a/chips/master.tag
1
chips.prt
tags/0.5/librairies/polytech_ge/2n2222a/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
TIME=' Created/Modified on Thu May 12 14:32:45 2005' ;
3
primitive '2N2222A';
4
  pin
5
    'E':
6
      PIN_NUMBER='(1)';
7
      PINUSE='UNSPEC';
8
      NO_LOAD_CHECK='BOTH';
9
      NO_IO_CHECK='BOTH';
10
      ALLOW_CONNECT='TRUE';
11
    'B':
12
      PIN_NUMBER='(2)';
13
      PINUSE='UNSPEC';
14
      NO_LOAD_CHECK='BOTH';
15
      NO_IO_CHECK='BOTH';
16
      ALLOW_CONNECT='TRUE';
17
    'C':
18
      PIN_NUMBER='(3)';
19
      PINUSE='UNSPEC';
20
      NO_LOAD_CHECK='BOTH';
21
      NO_IO_CHECK='BOTH';
22
      ALLOW_CONNECT='TRUE';
23
  end_pin;
24
  body
25
    CLASS='DISCRETE';
26
    PART_NAME='2N2222A';
27
    PHYS_DES_PREFIX='Q';
28
    JEDEC_TYPE='TO18';
29
    LAST_MODIFIED='MON OCT 5 13:48:08 1987';
30
    ABBREV='2N2222A';
31
    NEEDS_NO_SIZE='TRUE';
32
    LEADOUT_STYLE='TO18';
33
    PINCOUNT='3';
34
    PATH='10P';
35
    SIZE='1';
36
    BODY_NAME='2N2222a';
37
  end_body;
38
end_primitive;
39
END.
tags/0.5/librairies/polytech_ge/2n2222a/sym_1/master.tag
1
symbol.css
tags/0.5/librairies/polytech_ge/2n2222a/sym_1/symbol.css
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L -30 20 50 60 -1 0
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L -30 -20 50 -60 -1 0
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L -30 -50 -30 50 -1 0
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C 50 -100 "E\NAC" 50 -125 0 0 16 0 L
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C -50 0 "B\NAC" -50 10 0 0 16 0 R
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C 50 100 "C\NAC" 50 110 0 0 16 0 L
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P "NAME" "2N2222A" 70 43 0.00 0.00 32 0 0 0 0 0 1 0 0
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P "PATH" "?" 70 3 0.00 0.00 32 0 0 0 0 0 0 0 0
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P "$LOCATION" "?" 70 -37 0.00 0.00 32 0 0 0 0 0 1 0 0
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P "STATE" "ON" 55 -68 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "IC_VBE" "UNDEF" 55 -88 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "IC_VCE" "UNDEF" 55 -108 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "TOL_ON_OFF" "ON" 55 -128 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "RCA" "DEF" 55 -148 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "TEMP" "UNDEF" 55 -168 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "NEEDS_NO_SIZE" "TRUE" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
tags/0.5/librairies/polytech_ge/2n2222a/sym_2/master.tag
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symbol.css
tags/0.5/librairies/polytech_ge/2n2222a/sym_2/symbol.css
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L 50 60 50 100 -1 0
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L -30 -20 50 -60 -1 0
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L -30 -50 -30 50 -1 0
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C 50 100 "C\NAC" 50 110 0 0 16 0 L
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C -50 0 "B\NAC" -50 10 0 0 16 0 R
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C 50 -100 "E\NAC" 50 -125 0 0 16 0 L
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P "PATH" "?" 95 3 0.00 0.00 32 0 0 0 0 0 0 0 0
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P "$LOCATION" "?" 95 -37 0.00 0.00 32 0 0 0 0 0 1 0 0
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P "TOL_ON_OFF" "ON" 80 -128 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "RCA" "DEF" 80 -148 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "TEMP" "UNDEF" 80 -168 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "NEEDS_NO_SIZE" "TRUE" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
tags/0.5/librairies/polytech_ge/2n2222a/entity/master.tag
1
vhdl.vhd
tags/0.5/librairies/polytech_ge/2n2222a/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 00.01-s05 on May 12, 2005  14:32:48
tags/0.5/librairies/polytech_ge/2n2222a/entity/verilog.v
1
// generated by newgenasym  Thu May 12 14:32:48 2005
2

  
3

  
4
module \2n2222a  (b, c, e);
5
    inout b;
6
    inout c;
7
    inout e;
8

  
9

  
10
    initial
11
        begin
12
        end
13

  
14
endmodule
tags/0.5/librairies/polytech_ge/2n2222a/entity/vhdl.vhd
1
-- generated by newgenasym Thu May 12 14:32:48 2005
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity \2n2222a\ is
7
    port (    
8
	B:         INOUT  STD_LOGIC;    
9
	C:         INOUT  STD_LOGIC;    
10
	E:         INOUT  STD_LOGIC);
11
end \2n2222a\;
tags/0.5/librairies/polytech_ge/vcc_9v/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name VCC_BAR)
4
		(MSB )
5
		(LSB )
6
		(Type UNSPEC)
7
		(Location Bottom)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23

  
24
)
tags/0.5/librairies/polytech_ge/vcc_9v/metadata/master.tag
1
revision.dat
tags/0.5/librairies/polytech_ge/vcc_9v/metadata/revision.dat
1
(Cell	Vcc_9v
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		(Revision	0.0.5)
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11
		(Status	Created)
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		(ErrorStatus	0)
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15
		(CreateInfo	
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17
			(Time	10/21/09,14:19:32)
18

  
19
			(User	tchillet)
20

  
21
			(Path	ge.Vcc_9v)
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23
		)
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25
	)
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27
	(Views	
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29
		(View	Symbol
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31
			(Symbols	1
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33
				(Symbol	sym_1
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35
					(Symbol_Type	Normal)
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					(Max_Size	0)
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					(Checksum	000000003aa9330b)
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					(RevisionInfoBlock	
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						(Revision	0.0.2)
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						(ModificationStatus	NULL)
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49
						(Status	Created)
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51
						(ErrorStatus	0)
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53
						(CreateInfo	
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55
							(Time	10/21/09,14:23:14)
56

  
57
							(User	tchillet)
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							(Path	ge.vcc_12v)
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						)
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					)
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				)
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			)
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			(Checksum	000000001c9903a7)
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		)
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	)
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		(ToolName	PDV)
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		(Version	16.01-s021 (v16-1-53AR))
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		(License	PCB_librarian_expert)
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	)
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	(Checksum	000000001c530377)
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)
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tags/0.5/librairies/polytech_ge/vcc_9v/sym_1/master.tag
1
symbol.css
tags/0.5/librairies/polytech_ge/vcc_9v/sym_1/symbol.css
1
P "CDS_LMAN_SYM_OUTLINE" "-125,125,125,-125" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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L 25 0 -25 0 -1 0
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P "HDL_POWER" "Vcc_9v" -125 6 0 0 41 0 0 0 0 0 1 0 32
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P "BODY_TYPE" "PLUMBING" -45 -43 0 0 16 0 0 0 0 0 0 0 0
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L 0 0 0 -50 -1 0
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C 0 -50 "VCC_BAR" 5 -65 0 1 15 0 L
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tags/0.5/librairies/polytech_ge/cv2/chips/master.tag
1
chips.prt
tags/0.5/librairies/polytech_ge/cv2/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
TIME=' Created/Modified on Tue Jan 25 09:56:13 2005' ;
3
primitive 'CV2','CV2_THRU';
4
  pin
5
    'A':
6
      PIN_NUMBER='(1)';
7
      INPUT_LOAD='(-0.01,0.01)';
8
      OUTPUT_LOAD='(1.0,-1.0)';
9
      BIDIRECTIONAL='TRUE';
10
    'B':
11
      PIN_NUMBER='(2)';
12
      INPUT_LOAD='(-0.01,0.01)';
13
      OUTPUT_LOAD='(1.0,-1.0)';
14
      BIDIRECTIONAL='TRUE';
15
  end_pin;
16
  body
17
    CLASS='DISCRETE';
18
    PART_NAME='CV2';
19
    PHYS_DES_PREFIX='CAV';
20
    JEDEC_TYPE='CAV2';
21
    BODY_NAME='CV2';
22
  end_body;
23
end_primitive;
24
END.
tags/0.5/librairies/polytech_ge/cv2/sym_1/master.tag
1
symbol.css
tags/0.5/librairies/polytech_ge/cv2/sym_1/symbol.css
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L -50 75 50 75 -1 16
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L -50 50 -50 75 -1 16
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L 50 75 50 50 -1 16
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L 150 0 50 0 -1 -2
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L 50 0 50 25 -1 16
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C -150 0 "B" -172 0 0 1 22 0 R
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C 150 0 "A" 172 0 0 1 22 0 L
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P "PACK_TYPE" "THRU" -75 25 90.00 0.00 9 0 0 0 0 0 1 0 0
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0.00 0.00 22 0 0 0 0 0 0 0 0
tags/0.5/librairies/polytech_ge/cv2/entity/master.tag
1
vhdl.vhd
tags/0.5/librairies/polytech_ge/cv2/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 00.01-s05 on Jan 25, 2005  09:57:36
tags/0.5/librairies/polytech_ge/cv2/entity/verilog.v
1
// generated by newgenasym  Tue Jan 25 09:57:35 2005
2

  
3

  
4
module cv2 (a, b);
5
    inout a;
6
    inout b;
7

  
8

  
9
    initial
10
        begin
11
        end
12

  
13
endmodule
tags/0.5/librairies/polytech_ge/cv2/entity/vhdl.vhd
1
-- generated by newgenasym Tue Jan 25 09:57:35 2005
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity cv2 is
7
    port (    
8
	A:         INOUT  STD_LOGIC;    
9
	B:         INOUT  STD_LOGIC);
10
end cv2;
tags/0.5/librairies/polytech_ge/pnp/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name E)
4
		(MSB )
5
		(LSB )
6
		(Type ANALOG)
7
		(Location Bottom)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 1)
15
		(CheckAssert 1)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line-Dot)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name C)
25
		(MSB )
26
		(LSB )
27
		(Type ANALOG)
28
		(Location Top)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow )
32
		(OutputLoadHigh )
33
		(CheckLoad Off)
34
		(CheckIO Off)
35
		(CheckDir 1)
36
		(CheckAssert 1)
37
		(CheckOutput 0)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name B)
46
		(MSB )
47
		(LSB )
48
		(Type ANALOG)
49
		(Location Left)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow )
53
		(OutputLoadHigh )
54
		(CheckLoad Off)
55
		(CheckIO Off)
56
		(CheckDir 1)
57
		(CheckAssert 1)
58
		(CheckOutput 0)
59
		(UnknownLoading 0)
60
		(PinShape Line)
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65

  
66
)
tags/0.5/librairies/polytech_ge/pnp/metadata/master.tag
1
revision.dat
tags/0.5/librairies/polytech_ge/pnp/metadata/revision.dat
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		)
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	)
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	(Views	
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		(View	Symbol
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			(Symbols	1
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						(CreateInfo	
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							(Time	09/16/10,11:09:57)
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							(User	profs)
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						)
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						(LastModifyInfo	
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							(Time	09/16/10,11:09:48)
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							(User	profs)
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							(Path	_polytech_ge_beta.pnp)
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						)
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					)
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				)
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			)
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			(Checksum	000000001a2f034c)
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		)
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		(View	Chips
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			(Checksum	00000000a1279c49)
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			(Primitives	1
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					(RevisionInfoBlock	
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							(Time	09/16/10,11:09:57)
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							(User	profs)
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					(LogicalPhysicalPartRelation	
126

  
127
						(LogicalPart	pnp
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129
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131
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132

  
133
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147
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149
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152

  
153
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154

  
155
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157
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162

  
163
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167
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168

  
169
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171
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189
)
190

  
tags/0.5/librairies/polytech_ge/pnp/chips/master.tag
1
chips.prt
tags/0.5/librairies/polytech_ge/pnp/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'PNP_SMD';
3
  pin
4
    'E':
5
      PIN_NUMBER='(2)';
6
      PIN_TYPE='ANALOG';
7
      NO_LOAD_CHECK='Both';
8
      NO_IO_CHECK='Both';
9
      ALLOW_CONNECT='TRUE';
10
    'C':
11
      PIN_NUMBER='(3)';
12
      PIN_TYPE='ANALOG';
13
      NO_LOAD_CHECK='Both';
14
      NO_IO_CHECK='Both';
15
      ALLOW_CONNECT='TRUE';
16
    'B':
17
      PIN_NUMBER='(1)';
18
      PIN_TYPE='ANALOG';
19
      NO_LOAD_CHECK='Both';
20
      NO_IO_CHECK='Both';
21
      ALLOW_CONNECT='TRUE';
22
  end_pin;
23
  body
24
    PART_NAME='pnp';
25
    BODY_NAME='PNP';
26
    JEDEC_TYPE='sot23';
27
    PHYS_DES_PREFIX='T';
28
    CLASS='DISCRETE';
29
  end_body;
30
end_primitive;
31

  
32
END.
tags/0.5/librairies/polytech_ge/pnp/sym_1/master.tag
1
symbol.css
tags/0.5/librairies/polytech_ge/pnp/sym_1/symbol.css
1
P "CDS_LMAN_SYM_OUTLINE" "-50,100,50,-100" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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L 25 -75 0 -100 -1 16
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L 25 -75 0 -75 -1 16
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L -50 -50 50 -100 -1 16
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L 50 100 -50 50 -1 16
8
P "$VALUE" "?" -175 -124 0 0 22 0 0 0 0 0 1 0 0
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0 0 22 0 0 0 0 0 0 0 0
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X "PIN_TEXT" "B" -100 0 0 0 22 0 0 0 0 0 1 0 0
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23

  
tags/0.5/librairies/polytech_ge/pnp/entity/master.tag
1
verilog.v
tags/0.5/librairies/polytech_ge/pnp/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 16, 2010  11:09:57
tags/0.5/librairies/polytech_ge/pnp/entity/verilog.v
1
// generated by newgenasym  Thu Sep 16 11:09:57 2010
2

  
3

  
4
module pnp (b, c, e);
5
    inout b;
6
    inout c;
7
    inout e;
8

  
9

  
10
    initial
11
        begin
12
        end
13

  
14
endmodule
tags/0.5/librairies/polytech_ge/pnp/entity/vhdl.vhd
1
-- generated by newgenasym Thu Sep 16 11:09:57 2010
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity pnp is
7
    port (    
8
	B:         INOUT  STD_LOGIC;    
9
	C:         INOUT  STD_LOGIC;    
10
	E:         INOUT  STD_LOGIC);
11
end pnp;
tags/0.5/librairies/polytech_ge/potentiometre/chips/master.tag
1
chips.prt
tags/0.5/librairies/polytech_ge/potentiometre/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'POTENTIOMETRE','POTENTIOMETRE_T93YA';
3
  pin
4
    'IN':
5
      PIN_NUMBER='(1)';
6
      INPUT_LOAD='(-0.01,0.01)';
7
    'CUR':
8
      PIN_NUMBER='(2)';
9
      OUTPUT_LOAD='(1.0,-1.0)';
10
    'OUT':
11
      PIN_NUMBER='(3)';
12
      OUTPUT_LOAD='(1.0,-1.0)';
13
  end_pin;
14
  body
15
    PART_NAME='POTENTIOMETRE';
16
    BODY_NAME='POTENTIOMETRE';
17
    JEDEC_TYPE='pot_t93ya';
18
    PHYS_DES_PREFIX='P';
19
    CLASS='DISCRETE';
20
  end_body;
21
end_primitive;
22

  
23
primitive 'POTENTIOMETRE_X34A';
24
  pin
25
    'IN':
26
      PIN_NUMBER='(1)';
27
      INPUT_LOAD='(-0.01,0.01)';
28
    'CUR':
29
      PIN_NUMBER='(2)';
30
      OUTPUT_LOAD='(1.0,-1.0)';
31
    'OUT':
32
      PIN_NUMBER='(3)';
33
      OUTPUT_LOAD='(1.0,-1.0)';
34
  end_pin;
35
  body
36
    PART_NAME='POTENTIOMETRE';
37
    BODY_NAME='POTENTIOMETRE';
38
    JEDEC_TYPE='pot_x34a';
39
    PHYS_DES_PREFIX='P';
40
    CLASS='DISCRETE';
41
    NC_PINS='(4)';
42
  end_body;
43
end_primitive;
44

  
45
primitive 'POTENTIOMETRE_SIL3';
46
  pin
47
    'OUT':
48
      PIN_NUMBER='(3)';
49
      OUTPUT_LOAD='(1.0,-1.0)';
50
    'CUR':
51
      PIN_NUMBER='(2)';
52
      OUTPUT_LOAD='(1.0,-1.0)';
53
    'IN':
54
      PIN_NUMBER='(1)';
55
      INPUT_LOAD='(-0.01,0.01)';
56
  end_pin;
57
  body
58
    PART_NAME='POTENTIOMETRE';
59
    BODY_NAME='POTENTIOMETRE';
60
    JEDEC_TYPE='sil3';
61
    PHYS_DES_PREFIX='P';
62
    CLASS='DISCRETE';
63
  end_body;
64
end_primitive;
65

  
66
END.
tags/0.5/librairies/polytech_ge/potentiometre/sym_1/master.tag
1
symbol.css
tags/0.5/librairies/polytech_ge/potentiometre/sym_1/symbol.css
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21
P "NEEDS_NO_SIZE" "TRUE" -425 25 0.00 0.00 22 0 0 0 0 0 0 0 0
22
P "$PATH" "?" -50 0 0.00 0.00 22 0 0 0 0 0 0 0 0
tags/0.5/librairies/polytech_ge/potentiometre/entity/master.tag
1
vhdl.vhd
2
verilog.v
tags/0.5/librairies/polytech_ge/potentiometre/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Apr  1, 2008  09:41:15
tags/0.5/librairies/polytech_ge/potentiometre/entity/verilog.v
1
// generated by newgenasym  Tue Apr 01 09:41:15 2008
2

  
3

  
4
module potentiometre (cur, in, out);
5
    output cur;
6
    input in;
7
    output out;
8

  
9

  
10
    initial
11
        begin
12
        end
13

  
14
endmodule
tags/0.5/librairies/polytech_ge/potentiometre/entity/vhdl.vhd
1
-- generated by newgenasym Tue Apr 01 09:41:15 2008
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity potentiometre is
7
    port (    
8
	CUR:       OUT    STD_LOGIC;    
9
	\in\:      IN     STD_LOGIC;    
10
	\out\:     OUT    STD_LOGIC);
11
end potentiometre;
tags/0.5/librairies/polytech_ge/rj09_std/chips/master.tag
1
chips.prt
tags/0.5/librairies/polytech_ge/rj09_std/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
TIME=' Created/Modified on Mon Oct  9 11:02:33 2006' ;
3
primitive 'RJ11_STD_THRU';
4
  pin
5
    'A':
6
      PIN_NUMBER='(2)';
7
      PINUSE='UNSPEC';
8
      NO_LOAD_CHECK='BOTH';
9
      NO_IO_CHECK='BOTH';
10
      ALLOW_CONNECT='TRUE';
11
    'B':
12
      PIN_NUMBER='(3)';
13
      PINUSE='UNSPEC';
14
      NO_LOAD_CHECK='BOTH';
15
      NO_IO_CHECK='BOTH';
16
      ALLOW_CONNECT='TRUE';
17
    'C':
18
      PIN_NUMBER='(4)';
19
      PINUSE='UNSPEC';
20
      NO_LOAD_CHECK='BOTH';
21
      NO_IO_CHECK='BOTH';
22
      ALLOW_CONNECT='TRUE';
23
    'D':
24
      PIN_NUMBER='(5)';
25
      PINUSE='UNSPEC';
26
      NO_LOAD_CHECK='BOTH';
27
      NO_IO_CHECK='BOTH';
28
      ALLOW_CONNECT='TRUE';
29
  end_pin;
30
  body
31
    NC_PINS='(7,8,6,1)';
32
    CLASS='IO';
33
    PART_NAME='RJ11_STD';
34
    PHYS_DES_PREFIX='J';
35
    JEDEC_TYPE='RJ12_STD';
36
    BODY_NAME='RJ11_STD';
37
  end_body;
38
end_primitive;
39
END.
tags/0.5/librairies/polytech_ge/rj09_std/sym_1/master.tag
1
symbol.css
tags/0.5/librairies/polytech_ge/rj09_std/sym_1/symbol.css
1
L -150 -150 -150 150 -1 -2
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5
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6
L -200 50 -150 50 -1 -2
7
L -200 0 -150 0 -1 -2
8
L -200 -50 -150 -50 -1 -2
9
T 0 100 0.00 0.00 22 0 0 1 0 4 0
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RJ11
11
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19
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0.00 0.00 22 0 0 0 0 0 0 0 0
22
P "PART_NAME" "RJ11_STD" 25 125 0.00 0.00 22 0 0 0 0 0 0 0 0
23
P "PACK_TYPE" "THRU" 25 125 0.00 0.00 22 0 0 0 0 0 0 0 0
tags/0.5/librairies/polytech_ge/rj09_std/entity/master.tag
1
vhdl.vhd
tags/0.5/librairies/polytech_ge/rj09_std/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 00.01-s05 on Oct  9, 2006  11:02:37
tags/0.5/librairies/polytech_ge/rj09_std/entity/verilog.v
1
// generated by newgenasym  Mon Oct  9 11:02:36 2006
2

  
3

  
4
module rj09_std (a, b, c, d);
5
    inout a;
6
    inout b;
7
    inout c;
8
    inout d;
9

  
10

  
11
    initial
12
        begin
13
        end
14

  
15
endmodule
tags/0.5/librairies/polytech_ge/rj09_std/entity/vhdl.vhd
1
-- generated by newgenasym Mon Oct  9 11:02:36 2006
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity rj09_std is
7
    port (    
8
	A:         INOUT  STD_LOGIC;    
9
	B:         INOUT  STD_LOGIC;    
10
	C:         INOUT  STD_LOGIC;    
11
	D:         INOUT  STD_LOGIC);
12
end rj09_std;
tags/0.5/librairies/polytech_ge/vcc_#2d15v/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name VCC_BAR)
4
		(MSB )
5
		(LSB )
6
		(Type UNSPEC)
7
		(Location Bottom)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23

  
24
)
tags/0.5/librairies/polytech_ge/vcc_#2d15v/metadata/master.tag
1
revision.dat
tags/0.5/librairies/polytech_ge/vcc_#2d15v/metadata/revision.dat
1
(Cell	vcc_-15v
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3
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4

  
5
		(Baselined	0)
6

  
7
		(Revision	0.0.2)
8

  
9
		(ModificationStatus	NULL)
10

  
11
		(Status	Created)
12

  
13
		(ErrorStatus	0)
14

  
15
		(CreateInfo	
16

  
17
			(Time	10/21/09,14:47:39)
18

  
19
			(User	tchillet)
20

  
21
			(Path	ge.vcc_-15v)
22

  
23
		)
24

  
25
	)
26

  
27
	(Views	
28

  
29
		(View	Symbol
30

  
31
			(Symbols	1
32

  
33
				(Symbol	sym_1
34

  
35
					(Symbol_Type	Normal)
36

  
37
					(Max_Size	0)
38

  
39
					(Checksum	00000000b1683385)
40

  
41
					(RevisionInfoBlock	
42

  
43
						(Baselined	0)
44

  
45
						(Revision	0.0.2)
46

  
47
						(ModificationStatus	NULL)
48

  
49
						(Status	Created)
50

  
51
						(ErrorStatus	0)
52

  
53
						(CreateInfo	
54

  
55
							(Time	10/21/09,14:47:39)
56

  
57
							(User	tchillet)
58

  
59
							(Path	ge.vcc_-15v)
60

  
61
						)
62

  
63
					)
64

  
65
				)
66

  
67
			)
68

  
69
			(Checksum	000000001b9d0355)
70

  
71
		)
72

  
73
		(Checksum	000000001c48037e)
74

  
75
	)
76

  
77
	(VersionInfoBlock	
78

  
79
		(ToolName	PDV)
80

  
81
		(Version	16.01-s021 (v16-1-53AR))
82

  
83
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84

  
85
	)
86

  
87
	(Checksum	000000001b890380)
88

  
89
)
90

  
tags/0.5/librairies/polytech_ge/vcc_#2d15v/sym_1/master.tag
1
symbol.css
tags/0.5/librairies/polytech_ge/vcc_#2d15v/sym_1/symbol.css
1
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5
L 0 0 0 -50 -1 0
6
C 0 -50 "VCC_BAR" 5 -65 0 1 15 0 L
7

  
8

  
tags/0.5/librairies/polytech_ge/affich_cmg32122/chips/master.tag
1
chips.prt
tags/0.5/librairies/polytech_ge/affich_cmg32122/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
TIME=' Created/Modified on Mon Apr  3 12:23:42 2006' ;
3
primitive 'AFFICH_CMG32122_THRU';
4
  pin
5
    'A0':
6
      PIN_NUMBER='(4)';
7
      PINUSE='UNSPEC';
8
      NO_LOAD_CHECK='BOTH';
9
      NO_IO_CHECK='BOTH';
10
      ALLOW_CONNECT='TRUE';
11
    'CS1':
12
      PIN_NUMBER='(5)';
13
      PINUSE='UNSPEC';
14
      NO_LOAD_CHECK='BOTH';
15
      NO_IO_CHECK='BOTH';
16
      ALLOW_CONNECT='TRUE';
17
    'CS2':
18
      PIN_NUMBER='(6)';
19
      PINUSE='UNSPEC';
20
      NO_LOAD_CHECK='BOTH';
21
      NO_IO_CHECK='BOTH';
22
      ALLOW_CONNECT='TRUE';
23
    'VEE':
24
      PIN_NUMBER='(7)';
25
      PINUSE='UNSPEC';
26
      NO_LOAD_CHECK='BOTH';
27
      NO_IO_CHECK='BOTH';
... This diff was truncated because it exceeds the maximum size that can be displayed.

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