Revision 47

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trunk/librairies/polytech_ge/zener/sym_1/symbol.css
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C -100 0 "A" -122 0 0 1 22 0 R
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X "PIN_TEXT" "A" -75 0 0.00 0.00 11 0 0 0 0 0 1 0 0
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C 50 0 "K" 72 0 0 1 22 0 L
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X "PIN_TEXT" "K" 25 0 0.00 0.00 11 0 0 2 0 0 1 0 0
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X "PIN_TEXT" "K" 25 0 0.00 0.00 11 0 0 2 0 0 1 0 0
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X "PIN_TEXT" "A" -75 0 0.00 0.00 11 0 0 0 0 0 1 0 0
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P "$LOCATION" "?" -125 25 0.00 0.00 35 0 0 0 0 0 1 0 0
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P "PART_NAME" "DIODE_ZENER" -100 -50 0.00 0.00 11 0 0 0 0 0 1 0 0
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P "$PATH" "?" -150 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "NEEDS_NO_SIZE" "TRUE" -125 25 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "$VALUE" "?" 0 25 0.00 0.00 35 0 0 0 0 0 1 0 0
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P "PACK_TYPE" "SMD" -100 -25 0.00 0.00 11 0 0 0 0 0 1 0 0
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P "$VALUE" "?" 0 25 0.00 0.00 35 0 0 0 0 0 1 0 0
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P "NEEDS_NO_SIZE" "TRUE" -125 25 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "$PATH" "?" -150 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "PART_NAME" "DIODE_ZENER" -100 -50 0.00 0.00 11 0 0 0 0 0 1 0 0
trunk/librairies/polytech_ge/zener/entity/master.tag
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vhdl.vhd
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verilog.v
trunk/librairies/polytech_ge/zener/entity/verilog.v
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// generated by newgenasym  Wed Mar 30 11:11:34 2005
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// generated by newgenasym  Mon Sep 20 09:11:13 2010
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module zener (a, k);
trunk/librairies/polytech_ge/zener/entity/vhdl.vhd
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-- generated by newgenasym Wed Mar 30 11:11:34 2005
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-- generated by newgenasym Mon Sep 20 09:11:13 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity zener is
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entity ZENER is
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    port (    
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	A:         INOUT  STD_LOGIC;    
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	K:         INOUT  STD_LOGIC);
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end zener;
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end ZENER;

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