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-- generated by newgenasym Mon Sep 20 09:11:13 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity ZENER is
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    port (
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	A:         INOUT  STD_LOGIC;
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	K:         INOUT  STD_LOGIC);
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end ZENER;