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psd-data / trunk / librairies / polytech_ge_beta / cny17#2d2 / entity / vhdl.vhd @ 46

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-- generated by newgenasym Thu Sep 16 11:22:55 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity \cny17-2\ is
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    port (    
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	A:         INOUT  STD_LOGIC;    
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	B:         INOUT  STD_LOGIC;    
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	C:         INOUT  STD_LOGIC;    
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	E:         INOUT  STD_LOGIC;    
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	K:         INOUT  STD_LOGIC);
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end \cny17-2\;