Polytech CAO » Cadence_Pcb_Librairie

-- generated by newgenasym Thu Sep 16 11:22:55 2010

library ieee;

use     ieee.std_logic_1164.all;

use     work.all;

entity \cny17-2\ is

    port (    

	A:         INOUT  STD_LOGIC;    

	B:         INOUT  STD_LOGIC;    

	C:         INOUT  STD_LOGIC;    

	E:         INOUT  STD_LOGIC;    

	K:         INOUT  STD_LOGIC);

end \cny17-2\;