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psd-data / trunk / librairies / polytech_ge_beta / cny17#2d1 / entity / verilog.v @ 46

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// generated by newgenasym  Thu Sep 16 11:22:13 2010
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module \cny17-1  (a, b, c, e, k);
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    inout a;
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    inout b;
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    inout c;
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    inout e;
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    inout k;
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    initial
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        begin
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        end
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endmodule