Revision 46

View differences:

trunk/librairies/polytech_ge_beta/cny17#2d1/chips/master.tag
1
chips.prt
1
chips.prt
trunk/librairies/polytech_ge_beta/cny17#2d1/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
TIME='COMPILATION ON 3/13/2000 13:15:13 FROM OrCAD PART USING TransOLB.exe';
3
primitive 'CNY17-1';
4
  pin
5
    'A':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
9
      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(1)';
11
    'K':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(2)';
17
    'B':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(6)';
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    'E':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(4)';
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    'C':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(5)';
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  end_pin;
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  body
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    PART_NAME='CNY17-1';
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    PHYS_DES_PREFIX='U';
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    JEDEC_TYPE='DIP6';
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    BODY_NAME='CNY17-1';
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    CLASS='IC';
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    NC_PINS='(3,7,8)';
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  end_body;
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end_primitive;
45
END.
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'CNY17-1';
3
  pin
4
    'A':
5
      PIN_NUMBER='(1)';
6
      PIN_TYPE='ANALOG';
7
      NO_LOAD_CHECK='Both';
8
      NO_IO_CHECK='Both';
9
      ALLOW_CONNECT='TRUE';
10
    'K':
11
      PIN_NUMBER='(2)';
12
      PIN_TYPE='ANALOG';
13
      NO_LOAD_CHECK='Both';
14
      NO_IO_CHECK='Both';
15
      ALLOW_CONNECT='TRUE';
16
    'B':
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      PIN_NUMBER='(6)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
20
      NO_IO_CHECK='Both';
21
      ALLOW_CONNECT='TRUE';
22
    'E':
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      PIN_NUMBER='(4)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
27
      ALLOW_CONNECT='TRUE';
28
    'C':
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      PIN_NUMBER='(5)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      ALLOW_CONNECT='TRUE';
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  end_pin;
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  body
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    PART_NAME='CNY17-1';
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    BODY_NAME='CNY17-1';
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    JEDEC_TYPE='dip6_3';
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    PHYS_DES_PREFIX='U';
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    CLASS='IC';
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    NC_PINS='(3,7,8)';
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  end_body;
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end_primitive;
44

  
45
END.
trunk/librairies/polytech_ge_beta/cny17#2d1/entity/master.tag
1
verilog.v
1
verilog.v
trunk/librairies/polytech_ge_beta/cny17#2d1/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 1.06-s10 on Mar 13, 2000  13:15:17
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 16, 2010  11:22:13
trunk/librairies/polytech_ge_beta/cny17#2d1/entity/verilog.v
1
// generated by newgenasym  Mon Mar 13 13:15:16 2000
1
// generated by newgenasym  Thu Sep 16 11:22:13 2010
2 2

  
3 3

  
4 4
module \cny17-1  (a, b, c, e, k);
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    inout k;
6 5
    inout a;
7 6
    inout b;
7
    inout c;
8 8
    inout e;
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    inout c;
9
    inout k;
10 10

  
11 11

  
12 12
    initial
trunk/librairies/polytech_ge_beta/cny17#2d1/entity/vhdl.vhd
1
-- generated by newgenasym Mon Mar 13 13:15:16 2000
1
-- generated by newgenasym Thu Sep 16 11:22:13 2010
2 2

  
3 3
library ieee;
4 4
use     ieee.std_logic_1164.all;
trunk/librairies/polytech_ge_beta/cny17#2d2/chips/master.tag
1
chips.prt
1
chips.prt
trunk/librairies/polytech_ge_beta/cny17#2d2/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
TIME='COMPILATION ON 3/13/2000 13:15:19 FROM OrCAD PART USING TransOLB.exe';
3
primitive 'CNY17-2';
4
  pin
5
    'A':
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      PIN_TYPE='ANALOG';
7
      NO_LOAD_CHECK='BOTH';
8
      NO_IO_CHECK='BOTH';
9
      ALLOW_CONNECT='TRUE';
10
      PIN_NUMBER='(1)';
11
    'K':
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      PIN_TYPE='ANALOG';
13
      NO_LOAD_CHECK='BOTH';
14
      NO_IO_CHECK='BOTH';
15
      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(2)';
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    'B':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
21
      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(6)';
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    'E':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(4)';
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    'C':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(5)';
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  end_pin;
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  body
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    PART_NAME='CNY17-2';
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    PHYS_DES_PREFIX='U';
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    JEDEC_TYPE='DIP6';
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    BODY_NAME='CNY17-2';
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    CLASS='IC';
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    NC_PINS='(3,7,8)';
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  end_body;
44
end_primitive;
45
END.
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'CNY17-2';
3
  pin
4
    'A':
5
      PIN_NUMBER='(1)';
6
      PIN_TYPE='ANALOG';
7
      NO_LOAD_CHECK='Both';
8
      NO_IO_CHECK='Both';
9
      ALLOW_CONNECT='TRUE';
10
    'K':
11
      PIN_NUMBER='(2)';
12
      PIN_TYPE='ANALOG';
13
      NO_LOAD_CHECK='Both';
14
      NO_IO_CHECK='Both';
15
      ALLOW_CONNECT='TRUE';
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    'B':
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      PIN_NUMBER='(6)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
21
      ALLOW_CONNECT='TRUE';
22
    'E':
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      PIN_NUMBER='(4)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      ALLOW_CONNECT='TRUE';
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    'C':
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      PIN_NUMBER='(5)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      ALLOW_CONNECT='TRUE';
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  end_pin;
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  body
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    PART_NAME='CNY17-2';
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    BODY_NAME='CNY17-2';
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    JEDEC_TYPE='DIP6_3';
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    PHYS_DES_PREFIX='U';
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    CLASS='IC';
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    NC_PINS='(3,7,8)';
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  end_body;
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end_primitive;
44

  
45
END.
trunk/librairies/polytech_ge_beta/cny17#2d2/entity/master.tag
1
verilog.v
1
verilog.v
trunk/librairies/polytech_ge_beta/cny17#2d2/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 1.06-s10 on Mar 13, 2000  13:15:23
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 16, 2010  11:22:55
trunk/librairies/polytech_ge_beta/cny17#2d2/entity/verilog.v
1
// generated by newgenasym  Mon Mar 13 13:15:22 2000
1
// generated by newgenasym  Thu Sep 16 11:22:55 2010
2 2

  
3 3

  
4 4
module \cny17-2  (a, b, c, e, k);
5
    inout k;
6 5
    inout a;
7 6
    inout b;
7
    inout c;
8 8
    inout e;
9
    inout c;
9
    inout k;
10 10

  
11 11

  
12 12
    initial
trunk/librairies/polytech_ge_beta/cny17#2d2/entity/vhdl.vhd
1
-- generated by newgenasym Mon Mar 13 13:15:22 2000
1
-- generated by newgenasym Thu Sep 16 11:22:55 2010
2 2

  
3 3
library ieee;
4 4
use     ieee.std_logic_1164.all;

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