Revision 42

View differences:

trunk/librairies/polytech_ge/pnp/metadata/pinlist.txt
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(Pinlist
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	(Pin
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		(Name E)
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		(MSB )
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		(LSB )
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		(Type ANALOG)
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		(Location Bottom)
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		(InputLoadLow )
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		(InputLoadHigh )
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		(OutputLoadLow )
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		(OutputLoadHigh )
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		(CheckLoad Off)
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		(CheckIO Off)
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		(CheckDir 1)
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		(CheckAssert 1)
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		(CheckOutput 0)
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		(UnknownLoading 0)
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		(PinShape Line-Dot)
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		(DIFF_PAIR_PINS_POS )
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		(DIFF_PAIR_PINS_NEG )
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	)
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	(Pin
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		(Name C)
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		(MSB )
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		(LSB )
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		(Type ANALOG)
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		(Location Top)
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		(InputLoadLow )
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		(InputLoadHigh )
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		(OutputLoadLow )
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		(OutputLoadHigh )
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		(CheckLoad Off)
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		(CheckIO Off)
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		(CheckDir 1)
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		(CheckAssert 1)
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		(CheckOutput 0)
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		(UnknownLoading 0)
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		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
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		(DIFF_PAIR_PINS_NEG )
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	)
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	(Pin
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		(Name B)
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		(MSB )
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		(LSB )
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		(Type ANALOG)
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		(Location Left)
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		(InputLoadLow )
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		(InputLoadHigh )
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		(OutputLoadLow )
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		(OutputLoadHigh )
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		(CheckLoad Off)
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		(CheckIO Off)
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		(CheckDir 1)
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		(CheckAssert 1)
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		(CheckOutput 0)
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		(UnknownLoading 0)
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		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
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		(DIFF_PAIR_PINS_NEG )
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	)
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)
trunk/librairies/polytech_ge/pnp/metadata/master.tag
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revision.dat
trunk/librairies/polytech_ge/pnp/metadata/revision.dat
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(Cell	pnp
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	(RevisionInfoBlock	
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		(Baselined	0)
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		(Revision	0.0.1)
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		(ModificationStatus	NULL)
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		(Status	Created)
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		(ErrorStatus	0)
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		(CreateInfo	
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			(Time	09/16/10,11:09:57)
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			(User	profs)
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			(Path	_polytech_ge.pnp)
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		)
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		(LastModifyInfo	
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			(Time	09/16/10,11:09:48)
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			(User	profs)
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			(Path	_polytech_ge_beta.pnp)
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		)
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	)
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	(Views	
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		(View	Symbol
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			(Symbols	1
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				(Symbol	sym_1
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					(Symbol_Type	Normal)
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					(Max_Size	0)
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					(Checksum	000000004400832f)
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.1)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	09/16/10,11:09:57)
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							(User	profs)
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							(Path	_polytech_ge.pnp)
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						)
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						(LastModifyInfo	
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							(Time	09/16/10,11:09:48)
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							(User	profs)
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							(Path	_polytech_ge_beta.pnp)
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						)
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					)
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				)
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			)
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			(Checksum	000000001a2f034c)
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		)
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		(View	Chips
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			(Checksum	00000000a1279c49)
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			(Primitives	1
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				(Primitive	pnp_SMD
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.1)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	09/16/10,11:09:57)
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							(User	profs)
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							(Path	_polytech_ge.pnp)
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						)
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					)
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	pnp
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							(PackType	pnp_SMD)
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						)
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					)
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					(Packages	1
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						(FunctionGroups	1
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							(FunctionGroup	1[1]
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								(Linkages	
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									(Linkage	Symbol
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										(Name	sym_1)
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									)
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								)
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							)
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						)
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	sot23)
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							)
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						)
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					)
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				)
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			)
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		)
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		(Checksum	000000001d9703bd)
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	)
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	(VersionInfoBlock	
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		(ToolName	PDV)
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		(Version	16.01-s021 (v16-1-53AR))
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		(License	PCB_librarian_expert)
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	)
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	(Checksum	000000001bfe03af)
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)
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trunk/librairies/polytech_ge/pnp/chips/master.tag
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chips.prt
trunk/librairies/polytech_ge/pnp/chips/chips.prt
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FILE_TYPE=LIBRARY_PARTS;
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primitive 'PNP_SMD';
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  pin
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    'E':
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      PIN_NUMBER='(2)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      ALLOW_CONNECT='TRUE';
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    'C':
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      PIN_NUMBER='(3)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      ALLOW_CONNECT='TRUE';
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    'B':
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      PIN_NUMBER='(1)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      ALLOW_CONNECT='TRUE';
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  end_pin;
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  body
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    PART_NAME='pnp';
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    BODY_NAME='PNP';
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    JEDEC_TYPE='sot23';
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    PHYS_DES_PREFIX='T';
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    CLASS='DISCRETE';
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  end_body;
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end_primitive;
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END.
trunk/librairies/polytech_ge/pnp/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge/pnp/sym_1/symbol.css
1
P "CDS_LMAN_SYM_OUTLINE" "-50,100,50,-100" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
2
L -50 75 -50 -75 -1 16
3
L 25 -75 0 -100 -1 16
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L 25 -75 0 -75 -1 16
5
L 0 -100 0 -75 -1 16
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L -50 -50 50 -100 -1 16
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L 50 100 -50 50 -1 16
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P "$VALUE" "?" -175 -124 0 0 22 0 0 0 0 0 1 0 0
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0 0 22 0 0 0 0 0 0 0 0
10
P "$PATH" "?" 25 25 0 0 22 0 0 0 0 0 0 0 0
11
P "$LOCATION" "?" -100 150 0 0 22 0 0 0 0 0 1 0 0
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L 50 -100 50 -150 -1 0
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A 0 0 111 0 360 16
14
C 50 -150 "E" 72 -150 0 1 22 0 L
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X "PIN_TEXT" "E" 50 -75 0 0 22 0 0 2 0 0 1 0 0
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L 50 100 50 150 -1 0
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C 50 150 "C" 72 150 0 1 22 0 L
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X "PIN_TEXT" "C" 50 50 0 0 22 0 0 2 0 0 1 0 0
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L -150 0 -50 0 -1 0
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C -150 0 "B" -172 0 0 1 22 0 R
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X "PIN_TEXT" "B" -100 0 0 0 22 0 0 0 0 0 1 0 0
22

  
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trunk/librairies/polytech_ge/pnp/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge/pnp/entity/pc.db
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-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 16, 2010  11:09:57
trunk/librairies/polytech_ge/pnp/entity/verilog.v
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// generated by newgenasym  Thu Sep 16 11:09:57 2010
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module pnp (b, c, e);
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    inout b;
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    inout c;
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    inout e;
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    initial
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        begin
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        end
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endmodule
trunk/librairies/polytech_ge/pnp/entity/vhdl.vhd
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-- generated by newgenasym Thu Sep 16 11:09:57 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity pnp is
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    port (    
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	B:         INOUT  STD_LOGIC;    
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	C:         INOUT  STD_LOGIC;    
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	E:         INOUT  STD_LOGIC);
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end pnp;

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