Revision 359

View differences:

trunk/librairies/polytech_ge/q2n2905/chips/master.tag
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chips.prt
trunk/librairies/polytech_ge/q2n2905/chips/chips.prt
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FILE_TYPE=LIBRARY_PARTS;
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TIME='COMPILATION ON 3/7/2000 18:55:41 FROM OrCAD PART USING TransOLB.exe';
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primitive 'Q2N2905';
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  pin
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    'b':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(2)';
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    'c':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(3)';
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    'e':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(1)';
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  end_pin;
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  body
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    PART_NAME='Q2N2905';
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    PHYS_DES_PREFIX='Q';
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    JEDEC_TYPE='TO5';
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    BODY_NAME='Q2N2905';
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    CLASS='DISCRETE';
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  end_body;
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end_primitive;
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END.
trunk/librairies/polytech_ge/q2n2905/sym_1/master.tag
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symbol.css
trunk/librairies/polytech_ge/q2n2905/sym_1/symbol.css
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C 50 -150 "e" 75 -150 0 1 25 0 L
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X "Clock" "False" 50 -150 0.00 0.00 25 0 0 0 0 0 0 0 0
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C 50 50 "c" 75 50 0 1 25 0 L
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X "Clock" "False" 50 50 0.00 0.00 25 0 0 0 0 0 0 0 0
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C -50 -50 "b" -75 -50 0 1 25 0 L
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X "Clock" "False" -50 -50 0.00 0.00 25 0 0 0 0 0 0 0 0
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L 0 0 0 -100 -1 0
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L 50 -100 0 -75 -1 0
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L 50 0 0 -25 -1 0
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L -50 -50 0 -50 -1 0
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L 10 -80 35 -105 -1 0
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L 45 -85 10 -80 -1 0
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L 50 -150 50 -100 -1 0
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L 50 50 50 0 -1 0
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P "$LOCATION" "?" 0 50 0.00 0.00 47 0 0 2 0 0 1 0 2
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P "IMPLEMENTATION" "Q2N2905" -175 -175 0.00 0.00 25 0 0 0 0 0 1 0 0
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P "PATH" "?" -25 100 0.00 0.00 47 0 0 0 0 0 0 0 2
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P "IMPLEMENTATION_TYPE" "PSpice Model" 0 0 0.00 0.00 25 0 0 0 0 0 0 0 0
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P "IMPLEMENTATION_PATH" "" 0 0 0.00 0.00 25 0 0 0 0 0 0 0 0
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P "PSPICETEMPLATE" "Q^@REFDES %c %b %e @MODEL" 0 0 0.00 0.00 25 0 0 0 0 0 0 0 0
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P "COMPONENT" "2N2905" 0 0 0.00 0.00 25 0 0 0 0 0 0 0 0
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P "VALUE" "Q2N2905" 75 -100 0.00 0.00 25 0 0 0 0 0 0 0 0
trunk/librairies/polytech_ge/q2n2905/entity/master.tag
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vhdl.vhd
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verilog.v
trunk/librairies/polytech_ge/q2n2905/entity/pc.db
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-- pcdb file, Rev:1.0 written by VAN 1.06-s10 on Mar  7, 2000  18:55:46
trunk/librairies/polytech_ge/q2n2905/entity/verilog.v
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// generated by newgenasym  Mon Mar 06 16:15:54 2006
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module q2n2905 (b, c, e);
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    inout b;
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    inout c;
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    inout e;
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    initial
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        begin
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        end
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endmodule
trunk/librairies/polytech_ge/q2n2905/entity/vhdl.vhd
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-- generated by newgenasym Mon Mar 06 16:15:54 2006
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity Q2N2905 is
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    port (    
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	b:         INOUT  STD_LOGIC;    
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	c:         INOUT  STD_LOGIC;    
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	e:         INOUT  STD_LOGIC);
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end Q2N2905;
trunk/librairies/polytech_ge/q2n2905a/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge/q2n2905a/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
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TIME='COMPILATION ON 3/7/2000 18:44:17 FROM OrCAD PART USING TransOLB.exe';
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primitive 'Q2N2905A';
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  pin
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    'b':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(2)';
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    'c':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(3)';
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    'e':
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='BOTH';
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      NO_IO_CHECK='BOTH';
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      ALLOW_CONNECT='TRUE';
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      PIN_NUMBER='(1)';
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  end_pin;
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  body
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    PART_NAME='Q2N2905A';
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    PHYS_DES_PREFIX='Q';
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    JEDEC_TYPE='TO5';
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    BODY_NAME='Q2N2905A';
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    CLASS='DISCRETE';
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  end_body;
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end_primitive;
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END.
trunk/librairies/polytech_ge/q2n2905a/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge/q2n2905a/sym_1/symbol.css
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C 50 -150 "e" 75 -150 0 1 25 0 L
2
X "Clock" "False" 50 -150 0.00 0.00 25 0 0 0 0 0 0 0 0
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C 50 50 "c" 75 50 0 1 25 0 L
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X "Clock" "False" 50 50 0.00 0.00 25 0 0 0 0 0 0 0 0
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C -50 -50 "b" -75 -50 0 1 25 0 L
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X "Clock" "False" -50 -50 0.00 0.00 25 0 0 0 0 0 0 0 0
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L 0 0 0 -100 -1 0
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L 50 -100 0 -75 -1 0
9
L 50 0 0 -25 -1 0
10
L -50 -50 0 -50 -1 0
11
L 10 -80 35 -105 -1 0
12
L 45 -85 10 -80 -1 0
13
L 50 -150 50 -100 -1 0
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L 50 50 50 0 -1 0
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P "$LOCATION" "?" 0 50 0.00 0.00 47 0 0 2 0 0 1 0 2
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P "IMPLEMENTATION" "Q2N2905A" -200 -175 0.00 0.00 25 0 0 0 0 0 1 0 0
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P "PATH" "?" -25 100 0.00 0.00 47 0 0 0 0 0 0 0 2
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P "IMPLEMENTATION_TYPE" "PSpice Model" 0 0 0.00 0.00 25 0 0 0 0 0 0 0 0
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P "IMPLEMENTATION_PATH" "" 0 0 0.00 0.00 25 0 0 0 0 0 0 0 0
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P "PSPICETEMPLATE" "Q^@REFDES %c %b %e @MODEL" 0 0 0.00 0.00 25 0 0 0 0 0 0 0 0
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P "COMPONENT" "2N2905A" 0 0 0.00 0.00 25 0 0 0 0 0 0 0 0
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P "VALUE" "Q2N2905A" 75 -100 0.00 0.00 25 0 0 0 0 0 0 0 0
trunk/librairies/polytech_ge/q2n2905a/entity/master.tag
1
vhdl.vhd
2
verilog.v
trunk/librairies/polytech_ge/q2n2905a/entity/pc.db
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-- pcdb file, Rev:1.0 written by VAN 1.06-s10 on Mar  7, 2000  18:44:19
trunk/librairies/polytech_ge/q2n2905a/entity/verilog.v
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// generated by newgenasym  Mon Mar 06 16:15:42 2006
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module q2n2905a (b, c, e);
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    inout b;
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    inout c;
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    inout e;
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    initial
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        begin
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        end
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endmodule
trunk/librairies/polytech_ge/q2n2905a/entity/vhdl.vhd
1
-- generated by newgenasym Mon Mar 06 16:15:42 2006
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity Q2N2905A is
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    port (    
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	b:         INOUT  STD_LOGIC;    
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	c:         INOUT  STD_LOGIC;    
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	e:         INOUT  STD_LOGIC);
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end Q2N2905A;

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