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psd-data / trunk / librairies / polytech_ge_beta / adg3304 / entity / verilog.v @ 357

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// generated by newgenasym  Wed Oct 03 15:10:46 2012
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module adg3304 (a12, a23, a34, a45, en8, gnd7, vcc11, vcc214, y113, y212, y311,
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        y410);
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    inout a12;
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    inout a23;
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    inout a34;
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    inout a45;
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    input en8;
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    input gnd7;
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    input vcc11;
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    input vcc214;
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    inout y113;
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    inout y212;
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    inout y311;
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    inout y410;
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    initial
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        begin
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        end
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endmodule