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psd-data / trunk / librairies / polytech_ge_beta / 5sfh618 / entity / verilog.v @ 357

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// generated by newgenasym  Fri Oct 05 16:49:59 2012
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module \5sfh618  (a1, c4, e3, k2);
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    input a1;
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    input c4;
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    output e3;
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    output k2;
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    initial
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        begin
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        end
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endmodule