Revision 357

View differences:

trunk/librairies/polytech_ge_beta/bp_lph/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name A1)
4
		(MSB )
5
		(LSB )
6
		(Type BIDIR)
7
		(Location Left)
8
		(InputLoadLow -0.01)
9
		(InputLoadHigh 0.01)
10
		(OutputLoadLow 1.0)
11
		(OutputLoadHigh -1.0)
12
		(CheckLoad Both)
13
		(CheckIO Both)
14
		(CheckDir 1)
15
		(CheckAssert 1)
16
		(CheckOutput 1)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name B3)
25
		(MSB )
26
		(LSB )
27
		(Type BIDIR)
28
		(Location Right)
29
		(InputLoadLow -0.01)
30
		(InputLoadHigh 0.01)
31
		(OutputLoadLow 1.0)
32
		(OutputLoadHigh -1.0)
33
		(CheckLoad Both)
34
		(CheckIO Both)
35
		(CheckDir 1)
36
		(CheckAssert 1)
37
		(CheckOutput 1)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name A2)
46
		(MSB )
47
		(LSB )
48
		(Type BIDIR)
49
		(Location Left)
50
		(InputLoadLow -0.01)
51
		(InputLoadHigh 0.01)
52
		(OutputLoadLow 1.0)
53
		(OutputLoadHigh -1.0)
54
		(CheckLoad Both)
55
		(CheckIO Both)
56
		(CheckDir 1)
57
		(CheckAssert 1)
58
		(CheckOutput 1)
59
		(UnknownLoading 0)
60
		(PinShape Line)
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name B4)
67
		(MSB )
68
		(LSB )
69
		(Type BIDIR)
70
		(Location Right)
71
		(InputLoadLow -0.01)
72
		(InputLoadHigh 0.01)
73
		(OutputLoadLow 1.0)
74
		(OutputLoadHigh -1.0)
75
		(CheckLoad Both)
76
		(CheckIO Both)
77
		(CheckDir 1)
78
		(CheckAssert 1)
79
		(CheckOutput 1)
80
		(UnknownLoading 0)
81
		(PinShape Line)
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86

  
87
)
trunk/librairies/polytech_ge_beta/bp_lph/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge_beta/bp_lph/metadata/revision.dat
1
(Cell	bp_lph
2

  
3
	(RevisionInfoBlock	
4

  
5
		(Baselined	0)
6

  
7
		(Revision	0.0.9)
8

  
9
		(ModificationStatus	NULL)
10

  
11
		(Status	Created)
12

  
13
		(ErrorStatus	0)
14

  
15
		(CreateInfo	
16

  
17
			(Time	10/10/12,08:27:21)
18

  
19
			(User	fjullien)
20

  
21
			(Path	_polytech_ge_beta.bp_lph)
22

  
23
		)
24

  
25
		(LastModifyInfo	
26

  
27
			(Time	10/10/12,09:37:47)
28

  
29
			(User	fjullien)
30

  
31
			(Path	_polytech_ge_beta.bp_lph)
32

  
33
		)
34

  
35
	)
36

  
37
	(Views	
38

  
39
		(View	Symbol
40

  
41
			(Symbols	1
42

  
43
				(Symbol	sym_1
44

  
45
					(Symbol_Type	Normal)
46

  
47
					(Max_Size	0)
48

  
49
					(Checksum	00000000ab587c5c)
50

  
51
					(RevisionInfoBlock	
52

  
53
						(Baselined	0)
54

  
55
						(Revision	0.0.2)
56

  
57
						(ModificationStatus	NULL)
58

  
59
						(Status	Created)
60

  
61
						(ErrorStatus	0)
62

  
63
						(CreateInfo	
64

  
65
							(Time	10/10/12,09:36:52)
66

  
67
							(User	fjullien)
68

  
69
							(Path	_polytech_ge_beta.bp_lph)
70

  
71
						)
72

  
73
					)
74

  
75
				)
76

  
77
			)
78

  
79
			(Checksum	000000001dae03e3)
80

  
81
		)
82

  
83
		(View	Chips
84

  
85
			(Checksum	000000007df4a4a8)
86

  
87
			(Primitives	1
88

  
89
				(Primitive	BP_LPH
90

  
91
					(RevisionInfoBlock	
92

  
93
						(Baselined	0)
94

  
95
						(Revision	0.0.4)
96

  
97
						(ModificationStatus	NULL)
98

  
99
						(Status	Created)
100

  
101
						(ErrorStatus	0)
102

  
103
						(CreateInfo	
104

  
105
							(Time	10/10/12,08:27:52)
106

  
107
							(User	fjullien)
108

  
109
							(Path	_polytech_ge_beta.bp_lph)
110

  
111
						)
112

  
113
					)
114

  
115
					(LogicalPhysicalPartRelation	
116

  
117
						(LogicalPart	BP_LPH
118

  
119
							(PackType	BP_LPH)
120

  
121
						)
122

  
123
					)
124

  
125
					(Packages	1
126

  
127
						(FunctionGroups	1
128

  
129
							(FunctionGroup	1[1]
130

  
131
								(Linkages	
132

  
133
									(Linkage	Symbol
134

  
135
										(Name	sym_1)
136

  
137
									)
138

  
139
								)
140

  
141
							)
142

  
143
						)
144

  
145
						(Linkages	
146

  
147
							(DefaultFootPrint	
148

  
149
								(Name	LPH)
150

  
151
							)
152

  
153
						)
154

  
155
					)
156

  
157
				)
158

  
159
			)
160

  
161
		)
162

  
163
		(Checksum	000000001d8403e2)
164

  
165
	)
166

  
167
	(VersionInfoBlock	
168

  
169
		(ToolName	PDV)
170

  
171
		(Version	16.01-s021 (v16-1-53AR))
172

  
173
		(License	PCB_librarian_expert)
174

  
175
	)
176

  
177
	(Checksum	000000001bbd037c)
178

  
179
)
180

  
trunk/librairies/polytech_ge_beta/bp_lph/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge_beta/bp_lph/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'BP_LPH';
3
  pin
4
    'A1':
5
      PIN_NUMBER='(1)';
6
      BIDIRECTIONAL='TRUE';
7
      INPUT_LOAD='(-0.01,0.01)';
8
      OUTPUT_LOAD='(1.0,-1.0)';
9
    'A2':
10
      PIN_NUMBER='(2)';
11
      BIDIRECTIONAL='TRUE';
12
      INPUT_LOAD='(-0.01,0.01)';
13
      OUTPUT_LOAD='(1.0,-1.0)';
14
    'B3':
15
      PIN_NUMBER='(3)';
16
      BIDIRECTIONAL='TRUE';
17
      INPUT_LOAD='(-0.01,0.01)';
18
      OUTPUT_LOAD='(1.0,-1.0)';
19
    'B4':
20
      PIN_NUMBER='(4)';
21
      BIDIRECTIONAL='TRUE';
22
      INPUT_LOAD='(-0.01,0.01)';
23
      OUTPUT_LOAD='(1.0,-1.0)';
24
  end_pin;
25
  body
26
    PART_NAME='BP_LPH';
27
    BODY_NAME='BP_LPH';
28
    JEDEC_TYPE='LPH';
29
    PHYS_DES_PREFIX='U';
30
    CLASS='IC';
31
  end_body;
32
end_primitive;
33

  
34
END.
trunk/librairies/polytech_ge_beta/bp_lph/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge_beta/bp_lph/sym_1/symbol.css
1
P "CDS_LMAN_SYM_OUTLINE" "-125,125,125,-125" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
2
T -66 0 90 0 29 0 0 1 0 6 0
3
bp_lph
4
L 0 50 0 125 -1 0
5
L 0 -50 0 -125 -1 0
6
L -25 50 -25 -50 -1 0
7
L -25 25 -50 25 -1 0
8
L -50 25 -50 -25 -1 0
9
L -50 -25 -25 -25 -1 0
10
L 50 100 0 100 -1 0
11
L 50 -100 0 -100 -1 0
12
L 50 150 50 100 -1 0
13
C 50 150 "A1" 50 175 0 1 29 1 L
14
X "PIN_TEXT" "A1" 71 75 0 0 23 0 0 2 0 0 1 0 0
15
L 50 -150 50 -100 -1 0
16
C 50 -150 "B3" 50 -175 0 1 29 1 R
17
X "PIN_TEXT" "B3" 25 -100 0 0 23 0 0 0 0 0 1 0 0
18
L 0 150 0 100 -1 0
19
C 0 150 "A2" 0 175 0 1 29 1 L
20
X "PIN_TEXT" "A2" -4 75 0 0 23 0 0 2 0 0 1 0 0
21
L 0 -150 0 -100 -1 0
22
C 0 -150 "B4" 0 -175 0 1 29 1 R
23
X "PIN_TEXT" "B4" -50 -100 0 0 23 0 0 0 0 0 1 0 0
24

  
25

  
trunk/librairies/polytech_ge_beta/bp_lph/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge_beta/bp_lph/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct 10, 2012  10:06:54
trunk/librairies/polytech_ge_beta/bp_lph/entity/verilog.v
1
// generated by newgenasym  Wed Oct 10 10:06:54 2012
2

  
3

  
4
module bp_lph (a1, a2, b3, b4);
5
    inout a1;
6
    inout a2;
7
    inout b3;
8
    inout b4;
9

  
10

  
11
    initial
12
        begin
13
        end
14

  
15
endmodule
trunk/librairies/polytech_ge_beta/bp_lph/entity/vhdl.vhd
1
-- generated by newgenasym Wed Oct 10 10:06:54 2012
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity bp_lph is
7
    port (    
8
	A1:        INOUT  STD_LOGIC;    
9
	A2:        INOUT  STD_LOGIC;    
10
	B3:        INOUT  STD_LOGIC;    
11
	B4:        INOUT  STD_LOGIC);
12
end bp_lph;
trunk/librairies/polytech_ge_beta/5sfh618/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name A1)
4
		(MSB )
5
		(LSB )
6
		(Type INPUT)
7
		(Location Left)
8
		(InputLoadLow -0.01)
9
		(InputLoadHigh 0.01)
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Both)
13
		(CheckIO Both)
14
		(CheckDir 1)
15
		(CheckAssert 1)
16
		(CheckOutput 1)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name K2)
25
		(MSB )
26
		(LSB )
27
		(Type OUTPUT)
28
		(Location Right)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow 1.0)
32
		(OutputLoadHigh -1.0)
33
		(CheckLoad Both)
34
		(CheckIO Both)
35
		(CheckDir 1)
36
		(CheckAssert 1)
37
		(CheckOutput 1)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name E3)
46
		(MSB )
47
		(LSB )
48
		(Type OUTPUT)
49
		(Location Right)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow 1.0)
53
		(OutputLoadHigh -1.0)
54
		(CheckLoad Both)
55
		(CheckIO Both)
56
		(CheckDir 1)
57
		(CheckAssert 1)
58
		(CheckOutput 1)
59
		(UnknownLoading 0)
60
		(PinShape Line)
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name C4)
67
		(MSB )
68
		(LSB )
69
		(Type INPUT)
70
		(Location Left)
71
		(InputLoadLow -0.01)
72
		(InputLoadHigh 0.01)
73
		(OutputLoadLow )
74
		(OutputLoadHigh )
75
		(CheckLoad Both)
76
		(CheckIO Both)
77
		(CheckDir 1)
78
		(CheckAssert 1)
79
		(CheckOutput 1)
80
		(UnknownLoading 0)
81
		(PinShape Line)
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86

  
87
)
trunk/librairies/polytech_ge_beta/5sfh618/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge_beta/5sfh618/metadata/revision.dat
1
(Cell	5sfh618
2

  
3
	(RevisionInfoBlock	
4

  
5
		(Baselined	0)
6

  
7
		(Revision	0.0.4)
8

  
9
		(ModificationStatus	NULL)
10

  
11
		(Status	Created)
12

  
13
		(ErrorStatus	0)
14

  
15
		(CreateInfo	
16

  
17
			(Time	10/05/12,15:40:47)
18

  
19
			(User	fjullien)
20

  
21
			(Path	_polytech_ge_beta.5sfh618)
22

  
23
		)
24

  
25
		(LastModifyInfo	
26

  
27
			(Time	10/05/12,16:35:24)
28

  
29
			(User	fjullien)
30

  
31
			(Path	_polytech_ge_beta.5sfh618)
32

  
33
		)
34

  
35
	)
36

  
37
	(Views	
38

  
39
		(View	Symbol
40

  
41
			(Symbols	1
42

  
43
				(Symbol	sym_1
44

  
45
					(Symbol_Type	Normal)
46

  
47
					(Max_Size	0)
48

  
49
					(Checksum	000000005d3277fa)
50

  
51
					(RevisionInfoBlock	
52

  
53
						(Baselined	0)
54

  
55
						(Revision	0.0.3)
56

  
57
						(ModificationStatus	NULL)
58

  
59
						(Status	Created)
60

  
61
						(ErrorStatus	0)
62

  
63
						(CreateInfo	
64

  
65
							(Time	10/05/12,16:35:08)
66

  
67
							(User	fjullien)
68

  
69
							(Path	_polytech_ge_beta.5sfh618)
70

  
71
						)
72

  
73
					)
74

  
75
				)
76

  
77
			)
78

  
79
			(Checksum	000000001c0e03b4)
80

  
81
		)
82

  
83
		(View	Chips
84

  
85
			(Checksum	00000000fd107033)
86

  
87
			(Primitives	1
88

  
89
				(Primitive	5SFH618
90

  
91
					(RevisionInfoBlock	
92

  
93
						(Baselined	0)
94

  
95
						(Revision	0.0.1)
96

  
97
						(ModificationStatus	NULL)
98

  
99
						(Status	Created)
100

  
101
						(ErrorStatus	0)
102

  
103
						(CreateInfo	
104

  
105
							(Time	10/05/12,15:41:15)
106

  
107
							(User	fjullien)
108

  
109
							(Path	_polytech_ge_beta.5sfh618)
110

  
111
						)
112

  
113
					)
114

  
115
					(LogicalPhysicalPartRelation	
116

  
117
						(LogicalPart	5SFH618
118

  
119
							(PackType	5SFH618)
120

  
121
						)
122

  
123
					)
124

  
125
					(Packages	1
126

  
127
						(FunctionGroups	1
128

  
129
							(FunctionGroup	1[1]
130

  
131
								(Linkages	
132

  
133
									(Linkage	Symbol
134

  
135
										(Name	sym_1)
136

  
137
									)
138

  
139
								)
140

  
141
							)
142

  
143
						)
144

  
145
						(Linkages	
146

  
147
							(DefaultFootPrint	
148

  
149
								(Name	dip4_3)
150

  
151
							)
152

  
153
						)
154

  
155
					)
156

  
157
				)
158

  
159
			)
160

  
161
		)
162

  
163
		(Checksum	000000001b850388)
164

  
165
	)
166

  
167
	(VersionInfoBlock	
168

  
169
		(ToolName	PDV)
170

  
171
		(Version	16.01-s021 (v16-1-53AR))
172

  
173
		(License	PCB_librarian_expert)
174

  
175
	)
176

  
177
	(Checksum	000000001b600354)
178

  
179
)
180

  
trunk/librairies/polytech_ge_beta/5sfh618/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge_beta/5sfh618/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive '5SFH618';
3
  pin
4
    'A1':
5
      PIN_NUMBER='(1)';
6
      INPUT_LOAD='(-0.01,0.01)';
7
    'K2':
8
      PIN_NUMBER='(2)';
9
      OUTPUT_LOAD='(1.0,-1.0)';
10
    'E3':
11
      PIN_NUMBER='(3)';
12
      OUTPUT_LOAD='(1.0,-1.0)';
13
    'C4':
14
      PIN_NUMBER='(4)';
15
      INPUT_LOAD='(-0.01,0.01)';
16
  end_pin;
17
  body
18
    PART_NAME='5SFH618';
19
    BODY_NAME='5SFH618';
20
    JEDEC_TYPE='dip4_3';
21
    PHYS_DES_PREFIX='U';
22
    CLASS='IC';
23
  end_body;
24
end_primitive;
25

  
26
END.
trunk/librairies/polytech_ge_beta/5sfh618/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge_beta/5sfh618/sym_1/symbol.css
1
P "CDS_LMAN_SYM_OUTLINE" "-125,125,125,-125" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
2
L -125 125 -125 -125 -1 0
3
L -125 125 125 125 -1 0
4
L 125 125 125 -125 -1 0
5
L -125 -125 125 -125 -1 0
6
T -2 -125 0 0 29 0 0 1 0 7 0
7
5sfh618
8
L 0 100 0 -75 1 0
9
L -175 50 -125 50 -1 0
10
C -175 50 "A1" -200 50 0 1 29 0 R
11
X "PIN_TEXT" "A1" -115 50 0 0 23 0 0 0 0 0 1 0 0
12
L -175 -50 -125 -50 -1 0
13
C -175 -50 "K2" -200 -50 0 1 29 0 R
14
X "PIN_TEXT" "K2" -115 -50 0 0 23 0 0 0 0 0 1 0 0
15
L 175 -50 125 -50 -1 0
16
C 175 -50 "E3" 200 -50 0 1 29 0 L
17
X "PIN_TEXT" "E3" 115 -50 0 0 23 0 0 2 0 0 1 0 0
18
L 175 50 125 50 -1 0
19
C 175 50 "C4" 200 50 0 1 29 0 L
20
X "PIN_TEXT" "C4" 115 50 0 0 23 0 0 2 0 0 1 0 0
21

  
22

  
trunk/librairies/polytech_ge_beta/5sfh618/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge_beta/5sfh618/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct  5, 2012  16:49:59
trunk/librairies/polytech_ge_beta/5sfh618/entity/verilog.v
1
// generated by newgenasym  Fri Oct 05 16:49:59 2012
2

  
3

  
4
module \5sfh618  (a1, c4, e3, k2);
5
    input a1;
6
    input c4;
7
    output e3;
8
    output k2;
9

  
10

  
11
    initial
12
        begin
13
        end
14

  
15
endmodule
trunk/librairies/polytech_ge_beta/5sfh618/entity/vhdl.vhd
1
-- generated by newgenasym Fri Oct 05 16:49:59 2012
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity \5sfh618\ is
7
    port (    
8
	A1:        IN     STD_LOGIC;    
9
	C4:        IN     STD_LOGIC;    
10
	E3:        OUT    STD_LOGIC;    
11
	K2:        OUT    STD_LOGIC);
12
end \5sfh618\;
trunk/librairies/polytech_ge_beta/pcb/master.tag
1
self.dra
trunk/librairies/polytech_ge_beta/adg3304/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name VCC11)
4
		(MSB )
5
		(LSB )
6
		(Type POWER)
7
		(Location Left)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name A12)
25
		(MSB )
26
		(LSB )
27
		(Type BIDIR)
28
		(Location Left)
29
		(InputLoadLow -0.01)
30
		(InputLoadHigh 0.01)
31
		(OutputLoadLow 1.0)
32
		(OutputLoadHigh -1.0)
33
		(CheckLoad Both)
34
		(CheckIO Both)
35
		(CheckDir 1)
36
		(CheckAssert 1)
37
		(CheckOutput 1)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name A23)
46
		(MSB )
47
		(LSB )
48
		(Type BIDIR)
49
		(Location Left)
50
		(InputLoadLow -0.01)
51
		(InputLoadHigh 0.01)
52
		(OutputLoadLow 1.0)
53
		(OutputLoadHigh -1.0)
54
		(CheckLoad Both)
55
		(CheckIO Both)
56
		(CheckDir 1)
57
		(CheckAssert 1)
58
		(CheckOutput 1)
59
		(UnknownLoading 0)
60
		(PinShape Line)
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name A34)
67
		(MSB )
68
		(LSB )
69
		(Type BIDIR)
70
		(Location Left)
71
		(InputLoadLow -0.01)
72
		(InputLoadHigh 0.01)
73
		(OutputLoadLow 1.0)
74
		(OutputLoadHigh -1.0)
75
		(CheckLoad Both)
76
		(CheckIO Both)
77
		(CheckDir 1)
78
		(CheckAssert 1)
79
		(CheckOutput 1)
80
		(UnknownLoading 0)
81
		(PinShape Line)
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name A45)
88
		(MSB )
89
		(LSB )
90
		(Type BIDIR)
91
		(Location Left)
92
		(InputLoadLow -0.01)
93
		(InputLoadHigh 0.01)
94
		(OutputLoadLow 1.0)
95
		(OutputLoadHigh -1.0)
96
		(CheckLoad Both)
97
		(CheckIO Both)
98
		(CheckDir 1)
99
		(CheckAssert 1)
100
		(CheckOutput 1)
101
		(UnknownLoading 0)
102
		(PinShape Line)
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name GND7)
109
		(MSB )
110
		(LSB )
111
		(Type GROUND)
112
		(Location Left)
113
		(InputLoadLow )
114
		(InputLoadHigh )
115
		(OutputLoadLow )
116
		(OutputLoadHigh )
117
		(CheckLoad Off)
118
		(CheckIO Off)
119
		(CheckDir 0)
120
		(CheckAssert 0)
121
		(CheckOutput 0)
122
		(UnknownLoading 0)
123
		(PinShape Line)
124
		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
126
	)
127

  
128
	(Pin
129
		(Name VCC214)
130
		(MSB )
131
		(LSB )
132
		(Type POWER)
133
		(Location Right)
134
		(InputLoadLow )
135
		(InputLoadHigh )
136
		(OutputLoadLow )
137
		(OutputLoadHigh )
138
		(CheckLoad Off)
139
		(CheckIO Off)
140
		(CheckDir 0)
141
		(CheckAssert 0)
142
		(CheckOutput 0)
143
		(UnknownLoading 0)
144
		(PinShape Line)
145
		(DIFF_PAIR_PINS_POS )
146
		(DIFF_PAIR_PINS_NEG )
147
	)
148

  
149
	(Pin
150
		(Name Y113)
151
		(MSB )
152
		(LSB )
153
		(Type BIDIR)
154
		(Location Right)
155
		(InputLoadLow -0.01)
156
		(InputLoadHigh 0.01)
157
		(OutputLoadLow 1.0)
158
		(OutputLoadHigh -1.0)
159
		(CheckLoad Both)
160
		(CheckIO Both)
161
		(CheckDir 1)
162
		(CheckAssert 1)
163
		(CheckOutput 1)
164
		(UnknownLoading 0)
165
		(PinShape Line)
166
		(DIFF_PAIR_PINS_POS )
167
		(DIFF_PAIR_PINS_NEG )
168
	)
169

  
170
	(Pin
171
		(Name Y212)
172
		(MSB )
173
		(LSB )
174
		(Type BIDIR)
175
		(Location Right)
176
		(InputLoadLow -0.01)
177
		(InputLoadHigh 0.01)
178
		(OutputLoadLow 1.0)
179
		(OutputLoadHigh -1.0)
180
		(CheckLoad Both)
181
		(CheckIO Both)
182
		(CheckDir 1)
183
		(CheckAssert 1)
184
		(CheckOutput 1)
185
		(UnknownLoading 0)
186
		(PinShape Line)
187
		(DIFF_PAIR_PINS_POS )
188
		(DIFF_PAIR_PINS_NEG )
189
	)
190

  
191
	(Pin
192
		(Name Y311)
193
		(MSB )
194
		(LSB )
195
		(Type BIDIR)
196
		(Location Right)
197
		(InputLoadLow -0.01)
198
		(InputLoadHigh 0.01)
199
		(OutputLoadLow 1.0)
200
		(OutputLoadHigh -1.0)
201
		(CheckLoad Both)
202
		(CheckIO Both)
203
		(CheckDir 1)
204
		(CheckAssert 1)
205
		(CheckOutput 1)
206
		(UnknownLoading 0)
207
		(PinShape Line)
208
		(DIFF_PAIR_PINS_POS )
209
		(DIFF_PAIR_PINS_NEG )
210
	)
211

  
212
	(Pin
213
		(Name Y410)
214
		(MSB )
215
		(LSB )
216
		(Type BIDIR)
217
		(Location Right)
218
		(InputLoadLow -0.01)
219
		(InputLoadHigh 0.01)
220
		(OutputLoadLow 1.0)
221
		(OutputLoadHigh -1.0)
222
		(CheckLoad Both)
223
		(CheckIO Both)
224
		(CheckDir 1)
225
		(CheckAssert 1)
226
		(CheckOutput 1)
227
		(UnknownLoading 0)
228
		(PinShape Line)
229
		(DIFF_PAIR_PINS_POS )
230
		(DIFF_PAIR_PINS_NEG )
231
	)
232

  
233
	(Pin
234
		(Name EN8)
235
		(MSB )
236
		(LSB )
237
		(Type INPUT)
238
		(Location Right)
239
		(InputLoadLow -0.01)
240
		(InputLoadHigh 0.01)
241
		(OutputLoadLow )
242
		(OutputLoadHigh )
243
		(CheckLoad Both)
244
		(CheckIO Both)
245
		(CheckDir 1)
246
		(CheckAssert 1)
247
		(CheckOutput 1)
248
		(UnknownLoading 0)
249
		(PinShape Line)
250
		(DIFF_PAIR_PINS_POS )
251
		(DIFF_PAIR_PINS_NEG )
252
	)
253

  
254

  
255
)
trunk/librairies/polytech_ge_beta/adg3304/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge_beta/adg3304/metadata/revision.dat
1
(Cell	adg3304
2

  
3
	(RevisionInfoBlock	
4

  
5
		(Baselined	0)
6

  
7
		(Revision	0.0.9)
8

  
9
		(ModificationStatus	NULL)
10

  
11
		(Status	Created)
12

  
13
		(ErrorStatus	0)
14

  
15
		(CreateInfo	
16

  
17
			(Time	10/03/12,11:04:27)
18

  
19
			(User	fjullien)
20

  
21
			(Path	_polytech_ge_beta.adg3304)
22

  
23
		)
24

  
25
		(LastModifyInfo	
26

  
27
			(Time	10/03/12,11:46:57)
28

  
29
			(User	fjullien)
30

  
31
			(Path	_polytech_ge_beta.adg3304)
32

  
33
		)
34

  
35
	)
36

  
37
	(Views	
38

  
39
		(View	Symbol
40

  
41
			(Symbols	1
42

  
43
				(Symbol	sym_1
44

  
45
					(Symbol_Type	Normal)
46

  
47
					(Max_Size	0)
48

  
49
					(Checksum	0000000077f81864)
50

  
51
					(RevisionInfoBlock	
52

  
53
						(Baselined	0)
54

  
55
						(Revision	0.0.6)
56

  
57
						(ModificationStatus	NULL)
58

  
59
						(Status	Created)
60

  
61
						(ErrorStatus	0)
62

  
63
						(CreateInfo	
64

  
65
							(Time	10/03/12,11:46:18)
66

  
67
							(User	fjullien)
68

  
69
							(Path	_polytech_ge_beta.adg3304)
70

  
71
						)
72

  
73
					)
74

  
75
				)
76

  
77
			)
78

  
79
			(Checksum	000000001b910360)
80

  
81
		)
82

  
83
		(View	Chips
84

  
85
			(Checksum	000000003ca5b106)
86

  
87
			(Primitives	1
88

  
89
				(Primitive	ADG3304
90

  
91
					(RevisionInfoBlock	
92

  
93
						(Baselined	0)
94

  
95
						(Revision	0.0.3)
96

  
97
						(ModificationStatus	NULL)
98

  
99
						(Status	Created)
100

  
101
						(ErrorStatus	0)
102

  
103
						(CreateInfo	
104

  
105
							(Time	10/03/12,11:06:44)
106

  
107
							(User	fjullien)
108

  
109
							(Path	_polytech_ge_beta.adg3304)
110

  
111
						)
112

  
113
					)
114

  
115
					(LogicalPhysicalPartRelation	
116

  
117
						(LogicalPart	ADG3304
118

  
119
							(PackType	ADG3304)
120

  
121
						)
122

  
123
					)
124

  
125
					(Packages	1
126

  
127
						(FunctionGroups	1
128

  
129
							(FunctionGroup	1[1]
130

  
131
								(Linkages	
132

  
133
									(Linkage	Symbol
134

  
135
										(Name	sym_1)
136

  
137
									)
138

  
139
								)
140

  
141
							)
142

  
143
						)
144

  
145
						(Linkages	
146

  
147
							(DefaultFootPrint	
148

  
149
								(Name	TSSOP14)
150

  
151
							)
152

  
153
						)
154

  
155
					)
156

  
157
				)
158

  
159
			)
160

  
161
		)
162

  
163
		(Checksum	000000001b060359)
164

  
165
	)
166

  
167
	(VersionInfoBlock	
168

  
169
		(ToolName	PDV)
170

  
171
		(Version	16.01-s021 (v16-1-53AR))
172

  
173
		(License	PCB_librarian_expert)
174

  
175
	)
176

  
177
	(Checksum	000000001b30034b)
178

  
179
)
180

  
trunk/librairies/polytech_ge_beta/adg3304/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge_beta/adg3304/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'ADG3304';
3
  pin
4
    'VCC11':
5
      PIN_NUMBER='(1)';
6
      PINUSE='POWER';
7
      NO_LOAD_CHECK='Both';
8
      NO_IO_CHECK='Both';
9
      NO_ASSERT_CHECK='TRUE';
10
      NO_DIR_CHECK='TRUE';
11
      ALLOW_CONNECT='TRUE';
12
    'A12':
13
      PIN_NUMBER='(2)';
14
      BIDIRECTIONAL='TRUE';
15
      INPUT_LOAD='(-0.01,0.01)';
16
      OUTPUT_LOAD='(1.0,-1.0)';
17
    'A23':
18
      PIN_NUMBER='(3)';
19
      BIDIRECTIONAL='TRUE';
20
      INPUT_LOAD='(-0.01,0.01)';
21
      OUTPUT_LOAD='(1.0,-1.0)';
22
    'A34':
23
      PIN_NUMBER='(4)';
24
      BIDIRECTIONAL='TRUE';
25
      INPUT_LOAD='(-0.01,0.01)';
26
      OUTPUT_LOAD='(1.0,-1.0)';
27
    'A45':
28
      PIN_NUMBER='(5)';
29
      BIDIRECTIONAL='TRUE';
30
      INPUT_LOAD='(-0.01,0.01)';
31
      OUTPUT_LOAD='(1.0,-1.0)';
32
    'GND7':
33
      PIN_NUMBER='(7)';
34
      PINUSE='GROUND';
35
      NO_LOAD_CHECK='Both';
36
      NO_IO_CHECK='Both';
37
      NO_ASSERT_CHECK='TRUE';
38
      NO_DIR_CHECK='TRUE';
39
      ALLOW_CONNECT='TRUE';
40
    'VCC214':
41
      PIN_NUMBER='(14)';
42
      PINUSE='POWER';
43
      NO_LOAD_CHECK='Both';
44
      NO_IO_CHECK='Both';
45
      NO_ASSERT_CHECK='TRUE';
46
      NO_DIR_CHECK='TRUE';
47
      ALLOW_CONNECT='TRUE';
48
    'Y113':
49
      PIN_NUMBER='(13)';
50
      BIDIRECTIONAL='TRUE';
51
      INPUT_LOAD='(-0.01,0.01)';
52
      OUTPUT_LOAD='(1.0,-1.0)';
53
    'Y212':
54
      PIN_NUMBER='(12)';
55
      BIDIRECTIONAL='TRUE';
56
      INPUT_LOAD='(-0.01,0.01)';
57
      OUTPUT_LOAD='(1.0,-1.0)';
58
    'Y311':
59
      PIN_NUMBER='(11)';
60
      BIDIRECTIONAL='TRUE';
61
      INPUT_LOAD='(-0.01,0.01)';
62
      OUTPUT_LOAD='(1.0,-1.0)';
63
    'Y410':
64
      PIN_NUMBER='(10)';
65
      BIDIRECTIONAL='TRUE';
66
      INPUT_LOAD='(-0.01,0.01)';
67
      OUTPUT_LOAD='(1.0,-1.0)';
68
    'EN8':
69
      PIN_NUMBER='(8)';
70
      INPUT_LOAD='(-0.01,0.01)';
71
  end_pin;
72
  body
73
    PART_NAME='ADG3304';
74
    BODY_NAME='ADG3304';
75
    JEDEC_TYPE='TSSOP14';
76
    PHYS_DES_PREFIX='U';
77
    CLASS='IC';
78
    NC_PINS='(6,9)';
79
  end_body;
80
end_primitive;
81

  
82
END.
trunk/librairies/polytech_ge_beta/adg3304/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge_beta/adg3304/sym_1/symbol.css
1
P "CDS_LMAN_SYM_OUTLINE" "-150,175,150,-175" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
2
L -150 175 -150 -175 -1 0
3
L -150 175 150 175 -1 0
4
L 150 175 150 -175 -1 0
5
L -150 -175 150 -175 -1 0
6
T -2 -99 0 0 29 0 0 1 0 7 0
7
adg3304
8
L -100 225 -100 175 -1 0
9
C -100 225 "VCC11" -99 250 0 1 29 1 L
10
X "PIN_TEXT" "VCC1" -33 150 0 0 23 0 0 2 0 0 1 0 0
11
L -200 100 -150 100 -1 0
12
C -200 100 "A12" -225 100 0 1 29 0 R
13
X "PIN_TEXT" "A12" -140 100 0 0 23 0 0 0 0 0 1 0 0
14
L -200 50 -150 50 -1 0
15
C -200 50 "A23" -225 50 0 1 29 0 R
16
X "PIN_TEXT" "A23" -140 50 0 0 23 0 0 0 0 0 1 0 0
17
L -200 0 -150 0 -1 0
18
C -200 0 "A34" -225 0 0 1 29 0 R
19
X "PIN_TEXT" "A34" -140 0 0 0 23 0 0 0 0 0 1 0 0
20
L -200 -50 -150 -50 -1 0
21
C -200 -50 "A45" -225 -50 0 1 29 0 R
22
X "PIN_TEXT" "A45" -140 -50 0 0 23 0 0 0 0 0 1 0 0
23
L -100 -225 -100 -175 -1 0
24
C -100 -225 "GND7" -100 -250 0 1 29 1 R
25
X "PIN_TEXT" "GND1" -124 -149 0 0 23 0 0 0 0 0 1 0 0
26
L 100 225 100 175 -1 0
27
C 100 225 "VCC214" 100 250 0 1 29 1 L
28
X "PIN_TEXT" "VCC2" 138 150 0 0 23 0 0 2 0 0 1 0 0
29
L 200 100 150 100 -1 0
30
C 200 100 "Y113" 225 100 0 1 29 0 L
31
X "PIN_TEXT" "Y113" 140 100 0 0 23 0 0 2 0 0 1 0 0
32
L 200 50 150 50 -1 0
33
C 200 50 "Y212" 225 50 0 1 29 0 L
34
X "PIN_TEXT" "Y212" 140 50 0 0 23 0 0 2 0 0 1 0 0
35
L 200 0 150 0 -1 0
36
C 200 0 "Y311" 225 0 0 1 29 0 L
37
X "PIN_TEXT" "Y311" 140 0 0 0 23 0 0 2 0 0 1 0 0
38
L 200 -50 150 -50 -1 0
39
C 200 -50 "Y410" 225 -50 0 1 29 0 L
40
X "PIN_TEXT" "Y410" 140 -50 0 0 23 0 0 2 0 0 1 0 0
41
L 200 -150 150 -150 -1 0
42
C 200 -150 "EN8" 225 -150 0 1 29 0 L
43
X "PIN_TEXT" "EN8" 140 -150 0 0 23 0 0 2 0 0 1 0 0
44

  
45

  
trunk/librairies/polytech_ge_beta/adg3304/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge_beta/adg3304/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct  3, 2012  15:10:46
trunk/librairies/polytech_ge_beta/adg3304/entity/verilog.v
1
// generated by newgenasym  Wed Oct 03 15:10:46 2012
2

  
3

  
4
module adg3304 (a12, a23, a34, a45, en8, gnd7, vcc11, vcc214, y113, y212, y311,
5
        y410);
6
    inout a12;
7
    inout a23;
8
    inout a34;
9
    inout a45;
10
    input en8;
11
    input gnd7;
12
    input vcc11;
13
    input vcc214;
14
    inout y113;
... This diff was truncated because it exceeds the maximum size that can be displayed.

Also available in: Unified diff