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psd-data / trunk / librairies / polytech_ge_beta / pic18f4550 / entity / vhdl.vhd @ 352

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-- generated by newgenasym Thu May 31 16:44:33 2012
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity PIC18F4550 is
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    port (    
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	\mclr/vpp/re3\: IN     STD_LOGIC;    
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	\osc1/clki\: IN     STD_LOGIC;    
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	\osc2/clko/ra6\: OUT    STD_LOGIC;    
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	\ra0/an0\: INOUT  STD_LOGIC;    
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	\ra1/an1\: INOUT  STD_LOGIC;    
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	\ra2/an2/vref-/cvref\: INOUT  STD_LOGIC;    
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	\ra3/an3/vref+\: INOUT  STD_LOGIC;    
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	\ra4/t0cki/c1out/rcv\: INOUT  STD_LOGIC;    
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	\ra5/an4/ss/hlvdin/c2out\: INOUT  STD_LOGIC;    
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	\rb0/an12/int0/flt0/sdi/sda\: INOUT  STD_LOGIC;    
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	\rb1/an10/int1/sck/scl\: INOUT  STD_LOGIC;    
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	\rb2/an8/int2/vmo\: INOUT  STD_LOGIC;    
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	\rb3/an9/ccp2/vpo\: INOUT  STD_LOGIC;    
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	\rb4/an11/kbi0/csspp\: INOUT  STD_LOGIC;    
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	\rb5/kbi1/pgm\: INOUT  STD_LOGIC;    
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	\rb6/kbi2/pgc\: INOUT  STD_LOGIC;    
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	\rb7/kbi3/pgd\: INOUT  STD_LOGIC;    
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	\rc0/t1oso/t13cki\: INOUT  STD_LOGIC;    
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	\rc1/t1osi/ccp2/uoe\: INOUT  STD_LOGIC;    
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	\rc2/ccp1/p1a\: INOUT  STD_LOGIC;    
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	\rc4/d-/vm\: INOUT  STD_LOGIC;    
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	\rc5/d+/vp\: INOUT  STD_LOGIC;    
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	\rc6/tx/ck\: INOUT  STD_LOGIC;    
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	\rc7/rx/dt/sdo\: INOUT  STD_LOGIC;    
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	\rd0/spp0\: INOUT  STD_LOGIC;    
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	\rd1/spp1\: INOUT  STD_LOGIC;    
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	\rd2/spp2\: INOUT  STD_LOGIC;    
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	\rd3/spp3\: INOUT  STD_LOGIC;    
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	\rd4/spp4\: INOUT  STD_LOGIC;    
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	\rd5/spp5/p1b\: INOUT  STD_LOGIC;    
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	\rd6/spp6/p1c\: INOUT  STD_LOGIC;    
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	\rd7/spp7/p1d\: INOUT  STD_LOGIC;    
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	\re0/an5/ck1spp\: INOUT  STD_LOGIC;    
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	\re1/an6/ck2spp\: INOUT  STD_LOGIC;    
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	\re2/an7/oespp\: INOUT  STD_LOGIC;    
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	VDD:       IN     STD_LOGIC_VECTOR (1 DOWNTO 0);    
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	VSS:       IN     STD_LOGIC_VECTOR (1 DOWNTO 0);    
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	VUSB:      INOUT  STD_LOGIC);
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end PIC18F4550;