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psd-data / trunk / librairies / polytech_ge / cny74#2d4 / entity / vhdl.vhd @ 351

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-- generated by newgenasym Thu May 31 16:31:55 2012
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity \cny74-4\ is
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    port (    
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	A:         INOUT  STD_LOGIC_VECTOR (0 DOWNTO 0);    
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	C:         INOUT  STD_LOGIC_VECTOR (0 DOWNTO 0);    
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	E:         INOUT  STD_LOGIC_VECTOR (0 DOWNTO 0);    
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	K:         INOUT  STD_LOGIC_VECTOR (0 DOWNTO 0));
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end \cny74-4\;