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psd-data / trunk / librairies / polytech_ge / cny74#2d4 / entity / verilog.v @ 351

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// generated by newgenasym  Thu May 31 16:31:55 2012
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module \cny74-4  (a, c, e, k);
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    inout [0:0] a;
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    inout [0:0] c;
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    inout [0:0] e;
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    inout [0:0] k;
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    initial
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        begin
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        end
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endmodule