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psd-data / trunk / librairies / polytech_ge / 74f04 / entity / verilog.v @ 320

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// generated by newgenasym  Wed Oct 19 15:43:09 2011
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module \74f04  (a, \y* );
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    input a;
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    output \y* ;
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    initial
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        begin
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        end
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endmodule