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psd-data / trunk / librairies / polytech_ge / 74v1g32 / entity / verilog.v @ 307

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// generated by newgenasym  Fri Oct 07 15:30:00 2011
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module \74v1g32  (\1a , \1b , \1y , gnd, vcc);
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    input \1a ;
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    input \1b ;
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    output \1y ;
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    input gnd;
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    inout vcc;
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    initial
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        begin
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        end
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endmodule