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psd-data / trunk / librairies / polytech_ge_beta / pic18f1220 / entity / vhdl.vhd @ 300

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-- generated by newgenasym Fri Sep 23 16:20:50 2011
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity pic18f1220 is
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    port (    
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	\mclr/vpp/ra5\: IN     STD_LOGIC;    
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	\osc1/clk1/ra7\: INOUT  STD_LOGIC;    
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	\osc2/clk0/ra6\: INOUT  STD_LOGIC;    
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	\ra0/an0\: INOUT  STD_LOGIC;    
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	\ra1/lvdin/an1\: INOUT  STD_LOGIC;    
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	\ra2/an2/vref-\: INOUT  STD_LOGIC;    
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	\ra3/an3/vref+\: INOUT  STD_LOGIC;    
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	\ra4/t0cki\: INOUT  STD_LOGIC;    
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	\rb0/an4/int0\: INOUT  STD_LOGIC;    
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	\rb1/an5/tx/ck/int1\: INOUT  STD_LOGIC;    
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	\rb2/p1b/int2\: IN     STD_LOGIC;    
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	\rb3/ccp1/p1a\: INOUT  STD_LOGIC;    
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	\rb4/an6/rx/dt/kbi0\: INOUT  STD_LOGIC;    
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	\rb5/pgm/kbi1\: INOUT  STD_LOGIC;    
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	\rb6/pgc/t1oso/t13cki/p1c/kbi3\: INOUT  STD_LOGIC;    
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	\rb7/pgd/t1osi/p1d/kbi3\: INOUT  STD_LOGIC;    
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	\vcc/avdd\: IN     STD_LOGIC;    
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	\vss/avss\: IN     STD_LOGIC);
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end pic18f1220;