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psd-data / trunk / librairies / polytech_ge_beta / pic18f1220 / entity / verilog.v @ 300

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// generated by newgenasym  Fri Sep 23 16:20:50 2011
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module pic18f1220 (\mclr/vpp/ra5 , \osc1/clk1/ra7 , \osc2/clk0/ra6 , \ra0/an0 ,
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        \ra1/lvdin/an1 , \ra2/an2/vref- , \ra3/an3/vref+ , \ra4/t0cki ,
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        \rb0/an4/int0 , \rb1/an5/tx/ck/int1 , \rb2/p1b/int2 ,
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        \rb3/ccp1/p1a , \rb4/an6/rx/dt/kbi0 , \rb5/pgm/kbi1 ,
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        \rb6/pgc/t1oso/t13cki/p1c/kbi3 , \rb7/pgd/t1osi/p1d/kbi3 ,
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        \vcc/avdd , \vss/avss );
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    input \mclr/vpp/ra5 ;
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    inout \osc1/clk1/ra7 ;
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    inout \osc2/clk0/ra6 ;
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    inout \ra0/an0 ;
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    inout \ra1/lvdin/an1 ;
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    inout \ra2/an2/vref- ;
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    inout \ra3/an3/vref+ ;
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    inout \ra4/t0cki ;
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    inout \rb0/an4/int0 ;
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    inout \rb1/an5/tx/ck/int1 ;
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    input \rb2/p1b/int2 ;
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    inout \rb3/ccp1/p1a ;
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    inout \rb4/an6/rx/dt/kbi0 ;
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    inout \rb5/pgm/kbi1 ;
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    inout \rb6/pgc/t1oso/t13cki/p1c/kbi3 ;
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    inout \rb7/pgd/t1osi/p1d/kbi3 ;
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    input \vcc/avdd ;
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    input \vss/avss ;
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    initial
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        begin
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        end
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endmodule