Revision 300

View differences:

trunk/librairies/polytech_ge_beta/pic18f1220/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name RA0/AN0)
4
		(MSB )
5
		(LSB )
6
		(Type ANALOG)
7
		(Location Left)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name RA1/LVDIN/AN1)
25
		(MSB )
26
		(LSB )
27
		(Type ANALOG)
28
		(Location Left)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow )
32
		(OutputLoadHigh )
33
		(CheckLoad Off)
34
		(CheckIO Off)
35
		(CheckDir 0)
36
		(CheckAssert 0)
37
		(CheckOutput 0)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name RA4/T0CKI)
46
		(MSB )
47
		(LSB )
48
		(Type BIDIR)
49
		(Location Right)
50
		(InputLoadLow -0.01)
51
		(InputLoadHigh 0.01)
52
		(OutputLoadLow 1.0)
53
		(OutputLoadHigh -1.0)
54
		(CheckLoad Both)
55
		(CheckIO Both)
56
		(CheckDir 1)
57
		(CheckAssert 1)
58
		(CheckOutput 1)
59
		(UnknownLoading 0)
60
		(PinShape Line)
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name MCLR/VPP/RA5)
67
		(MSB )
68
		(LSB )
69
		(Type INPUT)
70
		(Location Left)
71
		(InputLoadLow -0.01)
72
		(InputLoadHigh 0.01)
73
		(OutputLoadLow )
74
		(OutputLoadHigh )
75
		(CheckLoad Both)
76
		(CheckIO Both)
77
		(CheckDir 1)
78
		(CheckAssert 1)
79
		(CheckOutput 1)
80
		(UnknownLoading 0)
81
		(PinShape Line)
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name VSS/AVSS)
88
		(MSB )
89
		(LSB )
90
		(Type GROUND)
91
		(Location Top)
92
		(InputLoadLow )
93
		(InputLoadHigh )
94
		(OutputLoadLow )
95
		(OutputLoadHigh )
96
		(CheckLoad Off)
97
		(CheckIO Off)
98
		(CheckDir 0)
99
		(CheckAssert 0)
100
		(CheckOutput 0)
101
		(UnknownLoading 0)
102
		(PinShape Line)
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name RA2/AN2/VREF-)
109
		(MSB )
110
		(LSB )
111
		(Type ANALOG)
112
		(Location Left)
113
		(InputLoadLow )
114
		(InputLoadHigh )
115
		(OutputLoadLow )
116
		(OutputLoadHigh )
117
		(CheckLoad Off)
118
		(CheckIO Off)
119
		(CheckDir 0)
120
		(CheckAssert 0)
121
		(CheckOutput 0)
122
		(UnknownLoading 0)
123
		(PinShape Line)
124
		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
126
	)
127

  
128
	(Pin
129
		(Name RA3/AN3/VREF+)
130
		(MSB )
131
		(LSB )
132
		(Type ANALOG)
133
		(Location Left)
134
		(InputLoadLow )
135
		(InputLoadHigh )
136
		(OutputLoadLow )
137
		(OutputLoadHigh )
138
		(CheckLoad Off)
139
		(CheckIO Off)
140
		(CheckDir 0)
141
		(CheckAssert 0)
142
		(CheckOutput 0)
143
		(UnknownLoading 0)
144
		(PinShape Line)
145
		(DIFF_PAIR_PINS_POS )
146
		(DIFF_PAIR_PINS_NEG )
147
	)
148

  
149
	(Pin
150
		(Name RB1/AN5/TX/CK/INT1)
151
		(MSB )
152
		(LSB )
153
		(Type ANALOG)
154
		(Location Left)
155
		(InputLoadLow )
156
		(InputLoadHigh )
157
		(OutputLoadLow )
158
		(OutputLoadHigh )
159
		(CheckLoad Off)
160
		(CheckIO Off)
161
		(CheckDir 0)
162
		(CheckAssert 0)
163
		(CheckOutput 0)
164
		(UnknownLoading 0)
165
		(PinShape Line)
166
		(DIFF_PAIR_PINS_POS )
167
		(DIFF_PAIR_PINS_NEG )
168
	)
169

  
170
	(Pin
171
		(Name RB4/AN6/RX/DT/KBI0)
172
		(MSB )
173
		(LSB )
174
		(Type ANALOG)
175
		(Location Left)
176
		(InputLoadLow )
177
		(InputLoadHigh )
178
		(OutputLoadLow )
179
		(OutputLoadHigh )
180
		(CheckLoad Off)
181
		(CheckIO Off)
182
		(CheckDir 0)
183
		(CheckAssert 0)
184
		(CheckOutput 0)
185
		(UnknownLoading 0)
186
		(PinShape Line)
187
		(DIFF_PAIR_PINS_POS )
188
		(DIFF_PAIR_PINS_NEG )
189
	)
190

  
191
	(Pin
192
		(Name RB5/PGM/KBI1)
193
		(MSB )
194
		(LSB )
195
		(Type BIDIR)
196
		(Location Right)
197
		(InputLoadLow -0.01)
198
		(InputLoadHigh 0.01)
199
		(OutputLoadLow 1.0)
200
		(OutputLoadHigh -1.0)
201
		(CheckLoad Both)
202
		(CheckIO Both)
203
		(CheckDir 1)
204
		(CheckAssert 1)
205
		(CheckOutput 1)
206
		(UnknownLoading 0)
207
		(PinShape Line)
208
		(DIFF_PAIR_PINS_POS )
209
		(DIFF_PAIR_PINS_NEG )
210
	)
211

  
212
	(Pin
213
		(Name RB6/PGC/T1OSO/T13CKI/P1C/KBI3)
214
		(MSB )
215
		(LSB )
216
		(Type BIDIR)
217
		(Location Right)
218
		(InputLoadLow -0.01)
219
		(InputLoadHigh 0.01)
220
		(OutputLoadLow 1.0)
221
		(OutputLoadHigh -1.0)
222
		(CheckLoad Both)
223
		(CheckIO Both)
224
		(CheckDir 1)
225
		(CheckAssert 1)
226
		(CheckOutput 1)
227
		(UnknownLoading 0)
228
		(PinShape Line)
229
		(DIFF_PAIR_PINS_POS )
230
		(DIFF_PAIR_PINS_NEG )
231
	)
232

  
233
	(Pin
234
		(Name RB7/PGD/T1OSI/P1D/KBI3)
235
		(MSB )
236
		(LSB )
237
		(Type BIDIR)
238
		(Location Right)
239
		(InputLoadLow -0.01)
240
		(InputLoadHigh 0.01)
241
		(OutputLoadLow 1.0)
242
		(OutputLoadHigh -1.0)
243
		(CheckLoad Both)
244
		(CheckIO Both)
245
		(CheckDir 1)
246
		(CheckAssert 1)
247
		(CheckOutput 1)
248
		(UnknownLoading 0)
249
		(PinShape Line)
250
		(DIFF_PAIR_PINS_POS )
251
		(DIFF_PAIR_PINS_NEG )
252
	)
253

  
254
	(Pin
255
		(Name OSC2/CLK0/RA6)
256
		(MSB )
257
		(LSB )
258
		(Type BIDIR)
259
		(Location Right)
260
		(InputLoadLow -0.01)
261
		(InputLoadHigh 0.01)
262
		(OutputLoadLow 1.0)
263
		(OutputLoadHigh -1.0)
264
		(CheckLoad Both)
265
		(CheckIO Both)
266
		(CheckDir 1)
267
		(CheckAssert 1)
268
		(CheckOutput 1)
269
		(UnknownLoading 0)
270
		(PinShape Line)
271
		(DIFF_PAIR_PINS_POS )
272
		(DIFF_PAIR_PINS_NEG )
273
	)
274

  
275
	(Pin
276
		(Name OSC1/CLK1/RA7)
277
		(MSB )
278
		(LSB )
279
		(Type BIDIR)
280
		(Location Right)
281
		(InputLoadLow -0.01)
282
		(InputLoadHigh 0.01)
283
		(OutputLoadLow 1.0)
284
		(OutputLoadHigh -1.0)
285
		(CheckLoad Both)
286
		(CheckIO Both)
287
		(CheckDir 1)
288
		(CheckAssert 1)
289
		(CheckOutput 1)
290
		(UnknownLoading 0)
291
		(PinShape Line)
292
		(DIFF_PAIR_PINS_POS )
293
		(DIFF_PAIR_PINS_NEG )
294
	)
295

  
296
	(Pin
297
		(Name RB2/P1B/INT2)
298
		(MSB )
299
		(LSB )
300
		(Type INPUT)
301
		(Location Left)
302
		(InputLoadLow -0.01)
303
		(InputLoadHigh 0.01)
304
		(OutputLoadLow )
305
		(OutputLoadHigh )
306
		(CheckLoad Both)
307
		(CheckIO Both)
308
		(CheckDir 1)
309
		(CheckAssert 1)
310
		(CheckOutput 1)
311
		(UnknownLoading 0)
312
		(PinShape Line)
313
		(DIFF_PAIR_PINS_POS )
314
		(DIFF_PAIR_PINS_NEG )
315
	)
316

  
317
	(Pin
318
		(Name RB3/CCP1/P1A)
319
		(MSB )
320
		(LSB )
321
		(Type BIDIR)
322
		(Location Right)
323
		(InputLoadLow -0.01)
324
		(InputLoadHigh 0.01)
325
		(OutputLoadLow 1.0)
326
		(OutputLoadHigh -1.0)
327
		(CheckLoad Both)
328
		(CheckIO Both)
329
		(CheckDir 1)
330
		(CheckAssert 1)
331
		(CheckOutput 1)
332
		(UnknownLoading 0)
333
		(PinShape Line)
334
		(DIFF_PAIR_PINS_POS )
335
		(DIFF_PAIR_PINS_NEG )
336
	)
337

  
338
	(Pin
339
		(Name RB0/AN4/INT0)
340
		(MSB )
341
		(LSB )
342
		(Type ANALOG)
343
		(Location Left)
344
		(InputLoadLow )
345
		(InputLoadHigh )
346
		(OutputLoadLow )
347
		(OutputLoadHigh )
348
		(CheckLoad Off)
349
		(CheckIO Off)
350
		(CheckDir 0)
351
		(CheckAssert 0)
352
		(CheckOutput 0)
353
		(UnknownLoading 0)
354
		(PinShape Line)
355
		(DIFF_PAIR_PINS_POS )
356
		(DIFF_PAIR_PINS_NEG )
357
	)
358

  
359
	(Pin
360
		(Name VCC/AVDD)
361
		(MSB )
362
		(LSB )
363
		(Type INPUT)
364
		(Location Left)
365
		(InputLoadLow -0.01)
366
		(InputLoadHigh 0.01)
367
		(OutputLoadLow )
368
		(OutputLoadHigh )
369
		(CheckLoad Both)
370
		(CheckIO Both)
371
		(CheckDir 1)
372
		(CheckAssert 1)
373
		(CheckOutput 1)
374
		(UnknownLoading 0)
375
		(PinShape Line)
376
		(DIFF_PAIR_PINS_POS )
377
		(DIFF_PAIR_PINS_NEG )
378
	)
379

  
380

  
381
)
trunk/librairies/polytech_ge_beta/pic18f1220/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge_beta/pic18f1220/metadata/revision.dat
1
(Cell	pic18f1220
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3
	(RevisionInfoBlock	
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5
		(Baselined	0)
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		(Revision	0.0.28)
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9
		(ModificationStatus	NULL)
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11
		(Status	Created)
12

  
13
		(ErrorStatus	0)
14

  
15
		(CreateInfo	
16

  
17
			(Time	09/21/11,16:30:59)
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19
			(User	rzhao)
20

  
21
			(Path	carte_mppt_lib.pic18f1220)
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23
		)
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		(LastModifyInfo	
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27
			(Time	09/23/11,15:21:40)
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29
			(User	rzhao)
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31
			(Path	carte_mppt_lib.pic18f1220)
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33
		)
34

  
35
	)
36

  
37
	(Views	
38

  
39
		(View	Symbol
40

  
41
			(Symbols	1
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43
				(Symbol	sym_1
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45
					(Symbol_Type	Normal)
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					(Max_Size	0)
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					(Checksum	00000000f42df1a8)
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.3)
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						(ModificationStatus	NULL)
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59
						(Status	Created)
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61
						(ErrorStatus	0)
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63
						(CreateInfo	
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65
							(Time	09/23/11,15:21:28)
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67
							(User	rzhao)
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							(Path	carte_mppt_lib.pic18f1220)
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						)
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					)
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				)
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			)
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			(Checksum	000000001db103e1)
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		)
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		(View	Chips
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			(Checksum	00000000ba28ca4c)
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87
			(Primitives	1
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89
				(Primitive	PIC18F1220
90

  
91
					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.6)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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105
							(Time	09/21/11,16:31:30)
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107
							(User	rzhao)
108

  
109
							(Path	carte_mppt_lib.pic18f1220)
110

  
111
						)
112

  
113
					)
114

  
115
					(LogicalPhysicalPartRelation	
116

  
117
						(LogicalPart	PIC18F1220
118

  
119
							(PackType	PIC18F1220)
120

  
121
						)
122

  
123
					)
124

  
125
					(Packages	1
126

  
127
						(FunctionGroups	1
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129
							(FunctionGroup	1[1]
130

  
131
								(Linkages	
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133
									(Linkage	Symbol
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135
										(Name	sym_1)
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									)
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							)
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						)
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	dip18_3)
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							)
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		(Checksum	000000001e690417)
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	(VersionInfoBlock	
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		(ToolName	PDV)
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		(Version	16.01-s021 (v16-1-53AR))
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		(License	PCB_librarian_expert)
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	)
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	(Checksum	000000001b710352)
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)
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trunk/librairies/polytech_ge_beta/pic18f1220/metadata/packages/PIC18F1220.list
1
RA0/AN0
2
RA1/LVDIN/AN1
3
RA4/T0CKI
4
MCLR/VPP/RA5
5
VSS/AVSS
6
RA2/AN2/VREF-
7
RA3/AN3/VREF+
8
RB0/AN4/INT0
9
RB1/AN5/TX/CK/INT1
10
RB4/AN6/RX/DT/KBI0
11
RB5/PGM/KBI1
12
RB6/PGC/T1OSO/T13CKI/P1C/KBI3
13
RB7/PGD/T1OSI/P1D/KBI3
14
VCC/AVDD
15
OSC2/CLK0/RA6
16
OSC1/CLK1/RA7
17
RB2/P1B/INT2
18
RB3/CCP1/P1A
trunk/librairies/polytech_ge_beta/pic18f1220/metadata/revision.log
1
	(Comment
2
		(Time 09/21/11,16:31:30)
3
		(User rzhao)
4
		(MsgId ECO_021)
5
		(Text "Package PIC18F1220 added to cell")
6
		(Param1 PIC18F1220)
7
	)
8
	(Comment
9
		(Time 09/23/11,13:48:32)
10
		(User rzhao)
11
		(MsgId ECO_081)
12
		(Text "Symbol sym_1 added to cell")
13
		(Param1 sym_1)
14
	)
15
	(Comment
16
		(Time 09/23/11,13:53:50)
17
		(User rzhao)
18
		(MsgId ECO_081)
19
		(Text "Symbol sym_2 added to cell")
20
		(Param1 sym_2)
21
	)
22
	(Comment
23
		(Time 09/23/11,14:16:22)
24
		(User rzhao)
25
		(MsgId ECO_081)
26
		(Text "Symbol sym_3 added to cell")
27
		(Param1 sym_3)
28
	)
29
	(Comment
30
		(Time 09/23/11,14:16:39)
31
		(User rzhao)
32
		(MsgId ECO_082)
33
		(Text "Symbol sym_2 deleted from cell")
34
		(Param1 sym_2)
35
	)
36
	(Comment
37
		(Time 09/23/11,14:17:12)
38
		(User rzhao)
39
		(MsgId ECO_082)
40
		(Text "Symbol sym_3 deleted from cell")
41
		(Param1 sym_3)
42
	)
43
	(Comment
44
		(Time 09/23/11,14:37:16)
45
		(User rzhao)
46
		(MsgId ECO_081)
47
		(Text "Symbol sym_2 added to cell")
48
		(Param1 sym_2)
49
	)
50
	(Comment
51
		(Time 09/23/11,14:37:25)
52
		(User rzhao)
53
		(MsgId ECO_082)
54
		(Text "Symbol sym_1 deleted from cell")
55
		(Param1 sym_1)
56
	)
57
	(Comment
58
		(Time 09/23/11,15:21:28)
59
		(User rzhao)
60
		(MsgId ECO_083)
61
		(Text "Symbol sym_2 renamed to sym_1")
62
		(Param1 sym_2)
63
		(Param2 sym_1)
64
	)
trunk/librairies/polytech_ge_beta/pic18f1220/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge_beta/pic18f1220/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'PIC18F1220';
3
  pin
4
    'RA0/AN0':
5
      PIN_NUMBER='(1)';
6
      PIN_TYPE='ANALOG';
7
      NO_LOAD_CHECK='Both';
8
      NO_IO_CHECK='Both';
9
      NO_ASSERT_CHECK='TRUE';
10
      NO_DIR_CHECK='TRUE';
11
      ALLOW_CONNECT='TRUE';
12
    'RA1/LVDIN/AN1':
13
      PIN_NUMBER='(2)';
14
      PIN_TYPE='ANALOG';
15
      NO_LOAD_CHECK='Both';
16
      NO_IO_CHECK='Both';
17
      NO_ASSERT_CHECK='TRUE';
18
      NO_DIR_CHECK='TRUE';
19
      ALLOW_CONNECT='TRUE';
20
    'RA4/T0CKI':
21
      PIN_NUMBER='(3)';
22
      BIDIRECTIONAL='TRUE';
23
      INPUT_LOAD='(-0.01,0.01)';
24
      OUTPUT_LOAD='(1.0,-1.0)';
25
    'MCLR/VPP/RA5':
26
      PIN_NUMBER='(4)';
27
      INPUT_LOAD='(-0.01,0.01)';
28
    'VSS/AVSS':
29
      PIN_NUMBER='(5)';
30
      PINUSE='GROUND';
31
      NO_LOAD_CHECK='Both';
32
      NO_IO_CHECK='Both';
33
      NO_ASSERT_CHECK='TRUE';
34
      NO_DIR_CHECK='TRUE';
35
      ALLOW_CONNECT='TRUE';
36
    'RA2/AN2/VREF-':
37
      PIN_NUMBER='(6)';
38
      PIN_TYPE='ANALOG';
39
      NO_LOAD_CHECK='Both';
40
      NO_IO_CHECK='Both';
41
      NO_ASSERT_CHECK='TRUE';
42
      NO_DIR_CHECK='TRUE';
43
      ALLOW_CONNECT='TRUE';
44
    'RA3/AN3/VREF+':
45
      PIN_NUMBER='(7)';
46
      PIN_TYPE='ANALOG';
47
      NO_LOAD_CHECK='Both';
48
      NO_IO_CHECK='Both';
49
      NO_ASSERT_CHECK='TRUE';
50
      NO_DIR_CHECK='TRUE';
51
      ALLOW_CONNECT='TRUE';
52
    'RB1/AN5/TX/CK/INT1':
53
      PIN_NUMBER='(9)';
54
      PIN_TYPE='ANALOG';
55
      NO_LOAD_CHECK='Both';
56
      NO_IO_CHECK='Both';
57
      NO_ASSERT_CHECK='TRUE';
58
      NO_DIR_CHECK='TRUE';
59
      ALLOW_CONNECT='TRUE';
60
    'RB4/AN6/RX/DT/KBI0':
61
      PIN_NUMBER='(10)';
62
      PIN_TYPE='ANALOG';
63
      NO_LOAD_CHECK='Both';
64
      NO_IO_CHECK='Both';
65
      NO_ASSERT_CHECK='TRUE';
66
      NO_DIR_CHECK='TRUE';
67
      ALLOW_CONNECT='TRUE';
68
    'RB5/PGM/KBI1':
69
      PIN_NUMBER='(11)';
70
      BIDIRECTIONAL='TRUE';
71
      INPUT_LOAD='(-0.01,0.01)';
72
      OUTPUT_LOAD='(1.0,-1.0)';
73
    'RB6/PGC/T1OSO/T13CKI/P1C/KBI3':
74
      PIN_NUMBER='(12)';
75
      BIDIRECTIONAL='TRUE';
76
      INPUT_LOAD='(-0.01,0.01)';
77
      OUTPUT_LOAD='(1.0,-1.0)';
78
    'RB7/PGD/T1OSI/P1D/KBI3':
79
      PIN_NUMBER='(13)';
80
      BIDIRECTIONAL='TRUE';
81
      INPUT_LOAD='(-0.01,0.01)';
82
      OUTPUT_LOAD='(1.0,-1.0)';
83
    'OSC2/CLK0/RA6':
84
      PIN_NUMBER='(15)';
85
      BIDIRECTIONAL='TRUE';
86
      INPUT_LOAD='(-0.01,0.01)';
87
      OUTPUT_LOAD='(1.0,-1.0)';
88
    'OSC1/CLK1/RA7':
89
      PIN_NUMBER='(16)';
90
      BIDIRECTIONAL='TRUE';
91
      INPUT_LOAD='(-0.01,0.01)';
92
      OUTPUT_LOAD='(1.0,-1.0)';
93
    'RB2/P1B/INT2':
94
      PIN_NUMBER='(17)';
95
      INPUT_LOAD='(-0.01,0.01)';
96
    'RB3/CCP1/P1A':
97
      PIN_NUMBER='(18)';
98
      BIDIRECTIONAL='TRUE';
99
      INPUT_LOAD='(-0.01,0.01)';
100
      OUTPUT_LOAD='(1.0,-1.0)';
101
    'RB0/AN4/INT0':
102
      PIN_NUMBER='(8)';
103
      PIN_TYPE='ANALOG';
104
      NO_LOAD_CHECK='Both';
105
      NO_IO_CHECK='Both';
106
      NO_ASSERT_CHECK='TRUE';
107
      NO_DIR_CHECK='TRUE';
108
      ALLOW_CONNECT='TRUE';
109
    'VCC/AVDD':
110
      PIN_NUMBER='(14)';
111
      INPUT_LOAD='(-0.01,0.01)';
112
  end_pin;
113
  body
114
    PART_NAME='PIC18F1220';
115
    BODY_NAME='PIC18F1220';
116
    JEDEC_TYPE='dip18_3';
117
    PHYS_DES_PREFIX='U';
118
    CLASS='IC';
119
  end_body;
120
end_primitive;
121

  
122
END.
trunk/librairies/polytech_ge_beta/pic18f1220/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge_beta/pic18f1220/sym_1/symbol.css
1
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L -550 275 550 275 -1 0
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L 550 275 550 -275 -1 0
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L -550 -275 550 -275 -1 0
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T 230 -225 0 0 57 0 0 1 0 10 0
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pic18f1220
8
L -600 200 -550 200 -1 0
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C -600 200 "RA0/AN0" -625 200 0 1 29 0 R
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L -600 150 -550 150 -1 0
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C -600 150 "RA1/LVDIN/AN1" -625 150 0 1 29 0 R
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X "PIN_TEXT" "RA1/LVDIN/AN1" -540 150 0 0 23 0 0 0 0 0 1 0 0
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L -600 0 -550 0 -1 0
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C -600 0 "RA4/T0CKI" -625 0 0 1 29 0 R
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X "PIN_TEXT" "RA4/T0CKI" -540 0 0 0 23 0 0 0 0 0 1 0 0
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L -600 -50 -550 -50 -1 0
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C -600 -50 "MCLR/VPP/RA5" -625 -50 0 1 29 0 R
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L 0 -325 0 -275 -1 0
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C 0 -325 "VSS/AVSS" 0 -350 0 1 29 1 R
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X "PIN_TEXT" "VSS/AVSS" -100 -275 0 0 23 0 0 0 0 0 1 0 0
23
L -600 100 -550 100 -1 0
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C -600 100 "RA2/AN2/VREF-" -625 100 0 1 29 0 R
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X "PIN_TEXT" "RA2/AN2/VREF-" -540 100 0 0 23 0 0 0 0 0 1 0 0
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L -600 50 -550 50 -1 0
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C -600 50 "RA3/AN3/VREF+" -625 50 0 1 29 0 R
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X "PIN_TEXT" "RA3/AN3/VREF+" -540 50 0 0 23 0 0 0 0 0 1 0 0
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L 600 -100 550 -100 -1 0
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C 600 -100 "RB1/AN5/TX/CK/INT1" 625 -100 0 1 29 0 L
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X "PIN_TEXT" "RB1/AN5/TX/CK/INT1" 540 -100 0 0 23 0 0 2 0 0 1 0 0
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L 600 50 550 50 -1 0
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C 600 50 "RB4/AN6/RX/DT/KBI0" 625 50 0 1 29 0 L
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X "PIN_TEXT" "RB4/AN6/RX/DT/KBI0" 540 50 0 0 23 0 0 2 0 0 1 0 0
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L 600 100 550 100 -1 0
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C 600 200 "RB7/PGD/T1OSI/P1D/KBI3" 625 200 0 1 29 0 L
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L -600 -200 -550 -200 -1 0
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C -600 -200 "OSC2/CLK0/RA6" -625 -200 0 1 29 0 R
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L -600 -150 -550 -150 -1 0
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C -600 -150 "OSC1/CLK1/RA7" -625 -150 0 1 29 0 R
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63

  
trunk/librairies/polytech_ge_beta/pic18f1220/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge_beta/pic18f1220/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 23, 2011  16:20:50
trunk/librairies/polytech_ge_beta/pic18f1220/entity/verilog.v
1
// generated by newgenasym  Fri Sep 23 16:20:50 2011
2

  
3

  
4
module pic18f1220 (\mclr/vpp/ra5 , \osc1/clk1/ra7 , \osc2/clk0/ra6 , \ra0/an0 ,
5
        \ra1/lvdin/an1 , \ra2/an2/vref- , \ra3/an3/vref+ , \ra4/t0cki ,
6
        \rb0/an4/int0 , \rb1/an5/tx/ck/int1 , \rb2/p1b/int2 ,
7
        \rb3/ccp1/p1a , \rb4/an6/rx/dt/kbi0 , \rb5/pgm/kbi1 ,
8
        \rb6/pgc/t1oso/t13cki/p1c/kbi3 , \rb7/pgd/t1osi/p1d/kbi3 ,
9
        \vcc/avdd , \vss/avss );
10
    input \mclr/vpp/ra5 ;
11
    inout \osc1/clk1/ra7 ;
12
    inout \osc2/clk0/ra6 ;
13
    inout \ra0/an0 ;
14
    inout \ra1/lvdin/an1 ;
15
    inout \ra2/an2/vref- ;
16
    inout \ra3/an3/vref+ ;
17
    inout \ra4/t0cki ;
18
    inout \rb0/an4/int0 ;
19
    inout \rb1/an5/tx/ck/int1 ;
20
    input \rb2/p1b/int2 ;
21
    inout \rb3/ccp1/p1a ;
22
    inout \rb4/an6/rx/dt/kbi0 ;
23
    inout \rb5/pgm/kbi1 ;
24
    inout \rb6/pgc/t1oso/t13cki/p1c/kbi3 ;
25
    inout \rb7/pgd/t1osi/p1d/kbi3 ;
26
    input \vcc/avdd ;
27
    input \vss/avss ;
28

  
29

  
30
    initial
31
        begin
32
        end
33

  
34
endmodule
trunk/librairies/polytech_ge_beta/pic18f1220/entity/vhdl.vhd
1
-- generated by newgenasym Fri Sep 23 16:20:50 2011
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity pic18f1220 is
7
    port (    
8
	\mclr/vpp/ra5\: IN     STD_LOGIC;    
9
	\osc1/clk1/ra7\: INOUT  STD_LOGIC;    
10
	\osc2/clk0/ra6\: INOUT  STD_LOGIC;    
11
	\ra0/an0\: INOUT  STD_LOGIC;    
12
	\ra1/lvdin/an1\: INOUT  STD_LOGIC;    
13
	\ra2/an2/vref-\: INOUT  STD_LOGIC;    
14
	\ra3/an3/vref+\: INOUT  STD_LOGIC;    
15
	\ra4/t0cki\: INOUT  STD_LOGIC;    
16
	\rb0/an4/int0\: INOUT  STD_LOGIC;    
17
	\rb1/an5/tx/ck/int1\: INOUT  STD_LOGIC;    
18
	\rb2/p1b/int2\: IN     STD_LOGIC;    
19
	\rb3/ccp1/p1a\: INOUT  STD_LOGIC;    
20
	\rb4/an6/rx/dt/kbi0\: INOUT  STD_LOGIC;    
21
	\rb5/pgm/kbi1\: INOUT  STD_LOGIC;    
22
	\rb6/pgc/t1oso/t13cki/p1c/kbi3\: INOUT  STD_LOGIC;    
23
	\rb7/pgd/t1osi/p1d/kbi3\: INOUT  STD_LOGIC;    
24
	\vcc/avdd\: IN     STD_LOGIC;    
25
	\vss/avss\: IN     STD_LOGIC);
26
end pic18f1220;

Also available in: Unified diff