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psd-data / trunk / librairies / polytech_ge_beta / max4172 / entity / verilog.v @ 299

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// generated by newgenasym  Fri Sep 23 17:20:57 2011
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module max4172 (gnd, nc1, nc2, out, pg, \rs+ , \rs- , \v+ );
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    input gnd;
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    inout nc1;
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    inout nc2;
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    output out;
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    output pg;
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    input \rs+ ;
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    input \rs- ;
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    input \v+ ;
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    initial
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        begin
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        end
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endmodule