Revision 299

View differences:

trunk/librairies/polytech_ge_beta/max4172/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name RS+)
4
		(MSB )
5
		(LSB )
6
		(Type INPUT)
7
		(Location Left)
8
		(InputLoadLow -0.01)
9
		(InputLoadHigh 0.01)
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
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	)
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23
	(Pin
24
		(Name RS-)
25
		(MSB )
26
		(LSB )
27
		(Type INPUT)
28
		(Location Left)
29
		(InputLoadLow -0.01)
30
		(InputLoadHigh 0.01)
31
		(OutputLoadLow )
32
		(OutputLoadHigh )
33
		(CheckLoad Off)
34
		(CheckIO Off)
35
		(CheckDir 0)
36
		(CheckAssert 0)
37
		(CheckOutput 0)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name NC2)
46
		(MSB )
47
		(LSB )
48
		(Type NC)
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		(Location Left)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow )
53
		(OutputLoadHigh )
54
		(CheckLoad Off)
55
		(CheckIO Off)
56
		(CheckDir 0)
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		(CheckAssert 0)
58
		(CheckOutput 0)
59
		(UnknownLoading 0)
60
		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
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	)
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	(Pin
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		(Name NC1)
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		(MSB )
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		(LSB )
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		(Type NC)
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		(Location Bottom)
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		(InputLoadLow )
72
		(InputLoadHigh )
73
		(OutputLoadLow )
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		(OutputLoadHigh )
75
		(CheckLoad Off)
76
		(CheckIO Off)
77
		(CheckDir 0)
78
		(CheckAssert 0)
79
		(CheckOutput 0)
80
		(UnknownLoading 0)
81
		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
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	(Pin
87
		(Name GND)
88
		(MSB )
89
		(LSB )
90
		(Type GROUND)
91
		(Location Right)
92
		(InputLoadLow )
93
		(InputLoadHigh )
94
		(OutputLoadLow )
95
		(OutputLoadHigh )
96
		(CheckLoad Off)
97
		(CheckIO Off)
98
		(CheckDir 0)
99
		(CheckAssert 0)
100
		(CheckOutput 0)
101
		(UnknownLoading 0)
102
		(PinShape Line)
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name OUT)
109
		(MSB )
110
		(LSB )
111
		(Type OUTPUT)
112
		(Location Right)
113
		(InputLoadLow )
114
		(InputLoadHigh )
115
		(OutputLoadLow 1.0)
116
		(OutputLoadHigh -1.0)
117
		(CheckLoad Both)
118
		(CheckIO Both)
119
		(CheckDir 1)
120
		(CheckAssert 1)
121
		(CheckOutput 1)
122
		(UnknownLoading 0)
123
		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
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	)
127

  
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	(Pin
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		(Name PG)
130
		(MSB )
131
		(LSB )
132
		(Type OUTPUT)
133
		(Location Right)
134
		(InputLoadLow )
135
		(InputLoadHigh )
136
		(OutputLoadLow 1.0)
137
		(OutputLoadHigh -1.0)
138
		(CheckLoad Both)
139
		(CheckIO Both)
140
		(CheckDir 1)
141
		(CheckAssert 1)
142
		(CheckOutput 1)
143
		(UnknownLoading 0)
144
		(PinShape Line)
145
		(DIFF_PAIR_PINS_POS )
146
		(DIFF_PAIR_PINS_NEG )
147
	)
148

  
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	(Pin
150
		(Name V+)
151
		(MSB )
152
		(LSB )
153
		(Type INPUT)
154
		(Location Right)
155
		(InputLoadLow -0.01)
156
		(InputLoadHigh 0.01)
157
		(OutputLoadLow )
158
		(OutputLoadHigh )
159
		(CheckLoad Both)
160
		(CheckIO Both)
161
		(CheckDir 1)
162
		(CheckAssert 1)
163
		(CheckOutput 1)
164
		(UnknownLoading 0)
165
		(PinShape Line)
166
		(DIFF_PAIR_PINS_POS )
167
		(DIFF_PAIR_PINS_NEG )
168
	)
169

  
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171
)
trunk/librairies/polytech_ge_beta/max4172/metadata/master.tag
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revision.dat
trunk/librairies/polytech_ge_beta/max4172/metadata/revision.dat
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(Cell	max4172
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	(RevisionInfoBlock	
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		(Baselined	0)
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		(Revision	0.0.3)
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		(ModificationStatus	NULL)
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		(Status	Created)
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		(ErrorStatus	0)
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		(CreateInfo	
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			(Time	09/23/11,16:34:48)
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			(User	rzhao)
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			(Path	_polytech_ge_beta.max4172)
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		)
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		(LastModifyInfo	
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			(Time	09/23/11,17:19:38)
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			(User	rzhao)
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			(Path	_polytech_ge_beta.max4172)
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		)
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	)
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	(Views	
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		(View	Symbol
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			(Symbols	1
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				(Symbol	sym_1
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					(Symbol_Type	Normal)
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					(Max_Size	0)
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					(Checksum	000000008941c606)
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.1)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	09/23/11,17:15:17)
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							(User	rzhao)
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							(Path	_polytech_ge_beta.max4172)
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						)
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					)
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				)
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			)
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			(Checksum	000000001b100356)
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		)
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		(View	Chips
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			(Checksum	00000000683106b7)
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			(Primitives	1
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				(Primitive	MAX4172
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.2)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	09/23/11,16:35:06)
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							(User	rzhao)
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							(Path	_polytech_ge_beta.max4172)
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						)
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					)
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	MAX4172
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							(PackType	MAX4172)
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						)
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					)
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					(Packages	1
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						(FunctionGroups	1
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							(FunctionGroup	1[1]
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								(Linkages	
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									(Linkage	Symbol
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										(Name	sym_1)
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									)
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								)
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							)
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						)
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	soic8)
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							)
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						)
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					)
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				)
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			)
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		(Checksum	000000001ac90376)
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	)
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	(VersionInfoBlock	
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		(ToolName	PDV)
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		(Version	16.01-s021 (v16-1-53AR))
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		(License	PCB_librarian_expert)
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	)
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	(Checksum	000000001c6b037f)
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)
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trunk/librairies/polytech_ge_beta/max4172/metadata/revision.log
1
	(Comment
2
		(Time 09/23/11,16:35:06)
3
		(User rzhao)
4
		(MsgId ECO_021)
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		(Text "Package MAX4172 added to cell")
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		(Param1 MAX4172)
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	)
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	(Comment
9
		(Time 09/23/11,16:45:30)
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		(User rzhao)
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		(MsgId ECO_021)
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		(Text "Package MAX4172_1 added to cell")
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		(Param1 MAX4172_1)
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	)
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	(Comment
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		(Time 09/23/11,16:45:39)
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		(User rzhao)
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		(MsgId ECO_022)
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		(Text "Package MAX4172_1 deleted from cell")
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		(Param1 MAX4172_1)
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	)
22
	(Comment
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		(Time 09/23/11,17:04:00)
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		(User rzhao)
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		(MsgId ECO_081)
26
		(Text "Symbol sym_1 added to cell")
27
		(Param1 sym_1)
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	)
29
	(Comment
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		(Time 09/23/11,17:15:08)
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		(User rzhao)
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		(MsgId ECO_082)
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		(Text "Symbol sym_1 deleted from cell")
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		(Param1 sym_1)
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	)
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	(Comment
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		(Time 09/23/11,17:15:17)
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		(User rzhao)
39
		(MsgId ECO_081)
40
		(Text "Symbol sym_1 added to cell")
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		(Param1 sym_1)
42
	)
trunk/librairies/polytech_ge_beta/max4172/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge_beta/max4172/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
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primitive 'MAX4172';
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  pin
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    'RS+':
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      PIN_NUMBER='(1)';
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      INPUT_LOAD='(-0.01,0.01)';
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    'RS-':
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      PIN_NUMBER='(2)';
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      INPUT_LOAD='(-0.01,0.01)';
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    'NC2':
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      PIN_NUMBER='(3)';
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      PINUSE='NC';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'NC1':
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      PIN_NUMBER='(4)';
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      PINUSE='NC';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'GND':
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      PIN_NUMBER='(5)';
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      PINUSE='GROUND';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'OUT':
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      PIN_NUMBER='(6)';
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      OUTPUT_LOAD='(1.0,-1.0)';
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    'PG':
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      PIN_NUMBER='(7)';
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      OUTPUT_LOAD='(1.0,-1.0)';
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    'V+':
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      PIN_NUMBER='(8)';
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      INPUT_LOAD='(-0.01,0.01)';
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  end_pin;
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  body
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    PART_NAME='MAX4172';
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    BODY_NAME='MAX4172';
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    JEDEC_TYPE='soic8';
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    PHYS_DES_PREFIX='U';
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    CLASS='IC';
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  end_body;
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end_primitive;
52

  
53
END.
trunk/librairies/polytech_ge_beta/max4172/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge_beta/max4172/sym_1/symbol.css
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P "CDS_LMAN_SYM_OUTLINE" "-125,125,125,-125" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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L -125 125 -125 -125 -1 0
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L -125 125 125 125 -1 0
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L 125 125 125 -125 -1 0
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L -125 -125 125 -125 -1 0
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T 23 -100 0 0 29 0 0 1 0 7 0
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max4172
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L -175 100 -125 100 -1 0
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C -175 100 "RS+" -200 100 0 1 29 0 R
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X "PIN_TEXT" "RS+" -115 100 0 0 23 0 0 0 0 0 1 0 0
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L -175 50 -125 50 -1 0
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C -175 50 "RS-" -200 50 0 1 29 0 R
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X "PIN_TEXT" "RS-" -115 50 0 0 23 0 0 0 0 0 1 0 0
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L 175 -50 125 -50 -1 0
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C 175 -50 "NC1" 200 -50 0 1 29 0 L
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X "PIN_TEXT" "NC1" 115 -50 0 0 23 0 0 2 0 0 1 0 0
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L 175 0 125 0 -1 0
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C 175 0 "NC2" 200 0 0 1 29 0 L
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X "PIN_TEXT" "NC2" 115 0 0 0 23 0 0 2 0 0 1 0 0
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L -100 -175 -100 -125 -1 0
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C -100 -175 "GND" -100 -200 0 1 29 1 R
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X "PIN_TEXT" "GND" -125 -125 0 0 23 0 0 0 0 0 1 0 0
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L 175 50 125 50 -1 0
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C 175 50 "OUT" 200 50 0 1 29 0 L
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X "PIN_TEXT" "OUT" 115 50 0 0 23 0 0 2 0 0 1 0 0
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L -175 -25 -125 -25 -1 0
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C -175 -25 "PG" -200 -25 0 1 29 0 R
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X "PIN_TEXT" "PG" -115 -25 0 0 23 0 0 0 0 0 1 0 0
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L 25 175 25 125 -1 0
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C 25 175 "V+" 25 200 0 1 29 1 L
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X "PIN_TEXT" "V+" 71 100 0 0 23 0 0 2 0 0 1 0 0
32

  
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trunk/librairies/polytech_ge_beta/max4172/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge_beta/max4172/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 23, 2011  17:20:57
trunk/librairies/polytech_ge_beta/max4172/entity/verilog.v
1
// generated by newgenasym  Fri Sep 23 17:20:57 2011
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module max4172 (gnd, nc1, nc2, out, pg, \rs+ , \rs- , \v+ );
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    input gnd;
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    inout nc1;
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    inout nc2;
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    output out;
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    output pg;
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    input \rs+ ;
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    input \rs- ;
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    input \v+ ;
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    initial
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        begin
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        end
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endmodule
trunk/librairies/polytech_ge_beta/max4172/entity/vhdl.vhd
1
-- generated by newgenasym Fri Sep 23 17:20:57 2011
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity max4172 is
7
    port (    
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	GND:       IN     STD_LOGIC;    
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	NC1:       INOUT  STD_LOGIC;    
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	NC2:       INOUT  STD_LOGIC;    
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	\out\:     OUT    STD_LOGIC;    
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	PG:        OUT    STD_LOGIC;    
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	\rs+\:     IN     STD_LOGIC;    
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	\rs-\:     IN     STD_LOGIC;    
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	\v+\:      IN     STD_LOGIC);
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end max4172;

Also available in: Unified diff