Revision 29

View differences:

trunk/librairies/polytech_ge/transformateur_2_2_sym/metadata/pinlist.txt
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(Pinlist
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	(Pin
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		(Name P1)
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		(MSB )
5
		(LSB )
6
		(Type ANALOG)
7
		(Location Left)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
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	)
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23
	(Pin
24
		(Name SP1)
25
		(MSB )
26
		(LSB )
27
		(Type ANALOG)
28
		(Location Left)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow )
32
		(OutputLoadHigh )
33
		(CheckLoad Off)
34
		(CheckIO Off)
35
		(CheckDir 0)
36
		(CheckAssert 0)
37
		(CheckOutput 0)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name SP2)
46
		(MSB )
47
		(LSB )
48
		(Type ANALOG)
49
		(Location Left)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow )
53
		(OutputLoadHigh )
54
		(CheckLoad Off)
55
		(CheckIO Off)
56
		(CheckDir 0)
57
		(CheckAssert 0)
58
		(CheckOutput 0)
59
		(UnknownLoading 0)
60
		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
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	)
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	(Pin
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		(Name N1)
67
		(MSB )
68
		(LSB )
69
		(Type ANALOG)
70
		(Location Left)
71
		(InputLoadLow )
72
		(InputLoadHigh )
73
		(OutputLoadLow )
74
		(OutputLoadHigh )
75
		(CheckLoad Off)
76
		(CheckIO Off)
77
		(CheckDir 0)
78
		(CheckAssert 0)
79
		(CheckOutput 0)
80
		(UnknownLoading 0)
81
		(PinShape Line)
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name N2)
88
		(MSB )
89
		(LSB )
90
		(Type ANALOG)
91
		(Location Left)
92
		(InputLoadLow )
93
		(InputLoadHigh )
94
		(OutputLoadLow )
95
		(OutputLoadHigh )
96
		(CheckLoad Off)
97
		(CheckIO Off)
98
		(CheckDir 0)
99
		(CheckAssert 0)
100
		(CheckOutput 0)
101
		(UnknownLoading 0)
102
		(PinShape Line)
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name SN1)
109
		(MSB )
110
		(LSB )
111
		(Type ANALOG)
112
		(Location Left)
113
		(InputLoadLow )
114
		(InputLoadHigh )
115
		(OutputLoadLow )
116
		(OutputLoadHigh )
117
		(CheckLoad Off)
118
		(CheckIO Off)
119
		(CheckDir 0)
120
		(CheckAssert 0)
121
		(CheckOutput 0)
122
		(UnknownLoading 0)
123
		(PinShape Line)
124
		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
126
	)
127

  
128
	(Pin
129
		(Name SN2)
130
		(MSB )
131
		(LSB )
132
		(Type ANALOG)
133
		(Location Left)
134
		(InputLoadLow )
135
		(InputLoadHigh )
136
		(OutputLoadLow )
137
		(OutputLoadHigh )
138
		(CheckLoad Off)
139
		(CheckIO Off)
140
		(CheckDir 0)
141
		(CheckAssert 0)
142
		(CheckOutput 0)
143
		(UnknownLoading 0)
144
		(PinShape Line)
145
		(DIFF_PAIR_PINS_POS )
146
		(DIFF_PAIR_PINS_NEG )
147
	)
148

  
149
	(Pin
150
		(Name P2)
151
		(MSB )
152
		(LSB )
153
		(Type ANALOG)
154
		(Location Left)
155
		(InputLoadLow )
156
		(InputLoadHigh )
157
		(OutputLoadLow )
158
		(OutputLoadHigh )
159
		(CheckLoad Off)
160
		(CheckIO Off)
161
		(CheckDir 0)
162
		(CheckAssert 0)
163
		(CheckOutput 0)
164
		(UnknownLoading 0)
165
		(PinShape Line)
166
		(DIFF_PAIR_PINS_POS )
167
		(DIFF_PAIR_PINS_NEG )
168
	)
169

  
170

  
171
)
trunk/librairies/polytech_ge/transformateur_2_2_sym/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge/transformateur_2_2_sym/metadata/revision.dat
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	TRANSFORMATEUR_2_2_SYM
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trunk/librairies/polytech_ge/transformateur_2_2_sym/chips/master.tag
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chips.prt
trunk/librairies/polytech_ge/transformateur_2_2_sym/chips/chips.prt
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FILE_TYPE=LIBRARY_PARTS;
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primitive 'TRANSFORMATEUR_2_2_SYM_TES_1064';
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  pin
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    'P1':
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      PIN_NUMBER='(1)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'P2':
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      PIN_NUMBER='(3)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'N1':
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      PIN_NUMBER='(2)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'N2':
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      PIN_NUMBER='(4)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'SP1':
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      PIN_NUMBER='(5)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'SP2':
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      PIN_NUMBER='(7)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'SN1':
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      PIN_NUMBER='(6)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'SN2':
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      PIN_NUMBER='(8)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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  end_pin;
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  body
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    PART_NAME='TRANSFORMATEUR_2_2_SYM';
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    JEDEC_TYPE='transfo_tes1064_2x110v_2x15v';
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    PHYS_DES_PREFIX='U';
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    CLASS='IC';
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  end_body;
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end_primitive;
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END.
trunk/librairies/polytech_ge/transformateur_2_2_sym/sym_1/master.tag
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trunk/librairies/polytech_ge/transformateur_2_2_sym/sym_1/symbol.css
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trunk/librairies/polytech_ge/transformateur_2_2_sym/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge/transformateur_2_2_sym/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 16, 2010  10:04:22
trunk/librairies/polytech_ge/transformateur_2_2_sym/entity/verilog.v
1
// generated by newgenasym  Thu Sep 16 10:04:22 2010
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module transformateur_2_2_sym (n1, n2, p1, p2, sn1, sn2, sp1, sp2);
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    inout n1;
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    inout n2;
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    inout p1;
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    inout p2;
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    inout sn1;
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    inout sn2;
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    inout sp1;
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    inout sp2;
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    initial
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        begin
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        end
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endmodule
trunk/librairies/polytech_ge/transformateur_2_2_sym/entity/vhdl.vhd
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-- generated by newgenasym Thu Sep 16 10:04:22 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity transformateur_2_2_sym is
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    port (    
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	N1:        INOUT  STD_LOGIC;    
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	N2:        INOUT  STD_LOGIC;    
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	P1:        INOUT  STD_LOGIC;    
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	P2:        INOUT  STD_LOGIC;    
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	SN1:       INOUT  STD_LOGIC;    
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	SN2:       INOUT  STD_LOGIC;    
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	SP1:       INOUT  STD_LOGIC;    
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	SP2:       INOUT  STD_LOGIC);
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end transformateur_2_2_sym;

Also available in: Unified diff