Revision 28

View differences:

trunk/librairies/polytech_ge/transformateur_1_2_sym/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name S1P)
4
		(MSB )
5
		(LSB )
6
		(Type UNSPEC)
7
		(Location Right)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name S2P)
25
		(MSB )
26
		(LSB )
27
		(Type UNSPEC)
28
		(Location Right)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow )
32
		(OutputLoadHigh )
33
		(CheckLoad Off)
34
		(CheckIO Off)
35
		(CheckDir 0)
36
		(CheckAssert 0)
37
		(CheckOutput 0)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name S2N)
46
		(MSB )
47
		(LSB )
48
		(Type UNSPEC)
49
		(Location Right)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow )
53
		(OutputLoadHigh )
54
		(CheckLoad Off)
55
		(CheckIO Off)
56
		(CheckDir 0)
57
		(CheckAssert 0)
58
		(CheckOutput 0)
59
		(UnknownLoading 0)
60
		(PinShape Line)
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name P)
67
		(MSB )
68
		(LSB )
69
		(Type ANALOG)
70
		(Location Left)
71
		(InputLoadLow )
72
		(InputLoadHigh )
73
		(OutputLoadLow )
74
		(OutputLoadHigh )
75
		(CheckLoad Off)
76
		(CheckIO Off)
77
		(CheckDir 0)
78
		(CheckAssert 0)
79
		(CheckOutput 0)
80
		(UnknownLoading 0)
81
		(PinShape Line)
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name N)
88
		(MSB )
89
		(LSB )
90
		(Type ANALOG)
91
		(Location Left)
92
		(InputLoadLow )
93
		(InputLoadHigh )
94
		(OutputLoadLow )
95
		(OutputLoadHigh )
96
		(CheckLoad Off)
97
		(CheckIO Off)
98
		(CheckDir 0)
99
		(CheckAssert 0)
100
		(CheckOutput 0)
101
		(UnknownLoading 0)
102
		(PinShape Line)
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name S1N)
109
		(MSB )
110
		(LSB )
111
		(Type UNSPEC)
112
		(Location Right)
113
		(InputLoadLow )
114
		(InputLoadHigh )
115
		(OutputLoadLow )
116
		(OutputLoadHigh )
117
		(CheckLoad Off)
118
		(CheckIO Off)
119
		(CheckDir 0)
120
		(CheckAssert 0)
121
		(CheckOutput 0)
122
		(UnknownLoading 0)
123
		(PinShape Line)
124
		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
126
	)
127

  
128

  
129
)
trunk/librairies/polytech_ge/transformateur_1_2_sym/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge/transformateur_1_2_sym/metadata/revision.dat
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			(Primitives	2
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	TRANSFORMATEUR_1_2_SYM
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trunk/librairies/polytech_ge/transformateur_1_2_sym/chips/master.tag
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chips.prt
trunk/librairies/polytech_ge/transformateur_1_2_sym/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'TRANSFORMATEUR_1_2_SYM_SPK';
3
  pin
4
    'S1P':
5
      PIN_NUMBER='(3)';
6
      PINUSE='UNSPEC';
7
      NO_LOAD_CHECK='Both';
8
      NO_IO_CHECK='Both';
9
      NO_ASSERT_CHECK='TRUE';
10
      NO_DIR_CHECK='TRUE';
11
      ALLOW_CONNECT='TRUE';
12
    'S2P':
13
      PIN_NUMBER='(5)';
14
      PINUSE='UNSPEC';
15
      NO_LOAD_CHECK='Both';
16
      NO_IO_CHECK='Both';
17
      NO_ASSERT_CHECK='TRUE';
18
      NO_DIR_CHECK='TRUE';
19
      ALLOW_CONNECT='TRUE';
20
    'S2N':
21
      PIN_NUMBER='(6)';
22
      PINUSE='UNSPEC';
23
      NO_LOAD_CHECK='Both';
24
      NO_IO_CHECK='Both';
25
      NO_ASSERT_CHECK='TRUE';
26
      NO_DIR_CHECK='TRUE';
27
      ALLOW_CONNECT='TRUE';
28
    'P':
29
      PIN_NUMBER='(1)';
30
      PIN_TYPE='ANALOG';
31
      NO_LOAD_CHECK='Both';
32
      NO_IO_CHECK='Both';
33
      NO_ASSERT_CHECK='TRUE';
34
      NO_DIR_CHECK='TRUE';
35
      ALLOW_CONNECT='TRUE';
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    'N':
37
      PIN_NUMBER='(2)';
38
      PIN_TYPE='ANALOG';
39
      NO_LOAD_CHECK='Both';
40
      NO_IO_CHECK='Both';
41
      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
44
    'S1N':
45
      PIN_NUMBER='(4)';
46
      PINUSE='UNSPEC';
47
      NO_LOAD_CHECK='Both';
48
      NO_IO_CHECK='Both';
49
      NO_ASSERT_CHECK='TRUE';
50
      NO_DIR_CHECK='TRUE';
51
      ALLOW_CONNECT='TRUE';
52
  end_pin;
53
  body
54
    PART_NAME='TRANSFORMATEUR_1_2_SYM';
55
    BODY_NAME='TRANSFORMATEUR_1_2_SYM';
56
    JEDEC_TYPE='transfo_spk';
57
    PHYS_DES_PREFIX='T';
58
    CLASS='IC';
59
  end_body;
60
end_primitive;
61

  
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primitive 'TRANSFORMATEUR_1_2_SYM_VCM';
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  pin
64
    'S1P':
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      PIN_NUMBER='(3)';
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      PINUSE='UNSPEC';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
69
      NO_ASSERT_CHECK='TRUE';
70
      NO_DIR_CHECK='TRUE';
71
      ALLOW_CONNECT='TRUE';
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    'S2P':
73
      PIN_NUMBER='(5)';
74
      PINUSE='UNSPEC';
75
      NO_LOAD_CHECK='Both';
76
      NO_IO_CHECK='Both';
77
      NO_ASSERT_CHECK='TRUE';
78
      NO_DIR_CHECK='TRUE';
79
      ALLOW_CONNECT='TRUE';
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    'S2N':
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      PIN_NUMBER='(6)';
82
      PINUSE='UNSPEC';
83
      NO_LOAD_CHECK='Both';
84
      NO_IO_CHECK='Both';
85
      NO_ASSERT_CHECK='TRUE';
86
      NO_DIR_CHECK='TRUE';
87
      ALLOW_CONNECT='TRUE';
88
    'P':
89
      PIN_NUMBER='(1)';
90
      PIN_TYPE='ANALOG';
91
      NO_LOAD_CHECK='Both';
92
      NO_IO_CHECK='Both';
93
      NO_ASSERT_CHECK='TRUE';
94
      NO_DIR_CHECK='TRUE';
95
      ALLOW_CONNECT='TRUE';
96
    'N':
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      PIN_NUMBER='(2)';
98
      PIN_TYPE='ANALOG';
99
      NO_LOAD_CHECK='Both';
100
      NO_IO_CHECK='Both';
101
      NO_ASSERT_CHECK='TRUE';
102
      NO_DIR_CHECK='TRUE';
103
      ALLOW_CONNECT='TRUE';
104
    'S1N':
105
      PIN_NUMBER='(4)';
106
      PINUSE='UNSPEC';
107
      NO_LOAD_CHECK='Both';
108
      NO_IO_CHECK='Both';
109
      NO_ASSERT_CHECK='TRUE';
110
      NO_DIR_CHECK='TRUE';
111
      ALLOW_CONNECT='TRUE';
112
  end_pin;
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  body
114
    PART_NAME='TRANSFORMATEUR_1_2_SYM';
115
    BODY_NAME='TRANSFORMATEUR_1_2_SYM';
116
    JEDEC_TYPE='transfo_vcm_2_24';
117
    PHYS_DES_PREFIX='U';
118
    CLASS='IC';
119
    NC_PINS='(7,8,9,10)';
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  end_body;
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end_primitive;
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123
END.
trunk/librairies/polytech_ge/transformateur_1_2_sym/sym_1/master.tag
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trunk/librairies/polytech_ge/transformateur_1_2_sym/sym_1/symbol.css
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trunk/librairies/polytech_ge/transformateur_1_2_sym/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge/transformateur_1_2_sym/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 16, 2010  09:47:39
trunk/librairies/polytech_ge/transformateur_1_2_sym/entity/verilog.v
1
// generated by newgenasym  Thu Sep 16 09:47:39 2010
2

  
3

  
4
module transformateur_1_2_sym (n, p, s1n, s1p, s2n, s2p);
5
    inout n;
6
    inout p;
7
    inout s1n;
8
    inout s1p;
9
    inout s2n;
10
    inout s2p;
11

  
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    initial
14
        begin
15
        end
16

  
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endmodule
trunk/librairies/polytech_ge/transformateur_1_2_sym/entity/vhdl.vhd
1
-- generated by newgenasym Thu Sep 16 09:47:39 2010
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library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity transformateur_1_2_sym is
7
    port (    
8
	N:         INOUT  STD_LOGIC;    
9
	P:         INOUT  STD_LOGIC;    
10
	S1N:       INOUT  STD_LOGIC;    
11
	S1P:       INOUT  STD_LOGIC;    
12
	S2N:       INOUT  STD_LOGIC;    
13
	S2P:       INOUT  STD_LOGIC);
14
end transformateur_1_2_sym;

Also available in: Unified diff