Statistics
| Revision:

psd-data / trunk / librairies / polytech_ge_beta / tda2822m / entity / verilog.v @ 273

History | View | Annotate | Download (290 Bytes)

1
// generated by newgenasym  Wed Sep 28 09:28:21 2011
2

    
3

    
4
module tda2822m (gnd, in1, in2, np1, np2, out1, out2, vcc);
5
    input gnd;
6
    input in1;
7
    input in2;
8
    inout np1;
9
    inout np2;
10
    output out1;
11
    output out2;
12
    input vcc;
13

    
14

    
15
    initial
16
        begin
17
        end
18

    
19
endmodule