Revision 273 trunk/librairies/polytech_ge_beta/tda2822m/entity/verilog.v

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verilog.v
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// generated by newgenasym  Wed Sep 21 17:08:27 2011
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// generated by newgenasym  Wed Sep 28 09:28:21 2011
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module tda2822m (gnd, in1, in2, np1, np2, out1, out2, vcc);

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