Revision 268

View differences:

trunk/librairies/polytech_ge_beta/tda2822m/cfg_analog/master.tag
1
expand.cfg
trunk/librairies/polytech_ge_beta/tda2822m/cfg_analog/expand.cfg
1
config tda2822m;
2
design _polytech_ge_beta.tda2822m:sch_1;
3
liblist standard, _polytech_ge, _polytech_ge_beta, rf_comp_lib;
4
viewlist awb_model, awb_dev, vhdla, vloga, spectrehdl, spice_1, sch_1, entity;
5
stoplist awb_model, awb_dev, vhdla, vloga, spectrehdl;
6
endconfig
trunk/librairies/polytech_ge_beta/tda2822m/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name OUT1)
4
		(MSB )
5
		(LSB )
6
		(Type OUTPUT)
7
		(Location Right)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow 1.0)
11
		(OutputLoadHigh -1.0)
12
		(CheckLoad Both)
13
		(CheckIO Both)
14
		(CheckDir 1)
15
		(CheckAssert 1)
16
		(CheckOutput 1)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name VCC)
25
		(MSB )
26
		(LSB )
27
		(Type POWER)
28
		(Location Top)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow )
32
		(OutputLoadHigh )
33
		(CheckLoad Off)
34
		(CheckIO Off)
35
		(CheckDir 0)
36
		(CheckAssert 0)
37
		(CheckOutput 0)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name OUT2)
46
		(MSB )
47
		(LSB )
48
		(Type OUTPUT)
49
		(Location Right)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow 1.0)
53
		(OutputLoadHigh -1.0)
54
		(CheckLoad Both)
55
		(CheckIO Both)
56
		(CheckDir 1)
57
		(CheckAssert 1)
58
		(CheckOutput 1)
59
		(UnknownLoading 0)
60
		(PinShape Line)
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name GND)
67
		(MSB )
68
		(LSB )
69
		(Type GROUND)
70
		(Location Bottom)
71
		(InputLoadLow )
72
		(InputLoadHigh )
73
		(OutputLoadLow )
74
		(OutputLoadHigh )
75
		(CheckLoad Off)
76
		(CheckIO Off)
77
		(CheckDir 0)
78
		(CheckAssert 0)
79
		(CheckOutput 0)
80
		(UnknownLoading 0)
81
		(PinShape Line)
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name NP2)
88
		(MSB )
89
		(LSB )
90
		(Type NC)
91
		(Location Left)
92
		(InputLoadLow )
93
		(InputLoadHigh )
94
		(OutputLoadLow )
95
		(OutputLoadHigh )
96
		(CheckLoad Off)
97
		(CheckIO Off)
98
		(CheckDir 0)
99
		(CheckAssert 0)
100
		(CheckOutput 0)
101
		(UnknownLoading 0)
102
		(PinShape Line)
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name IN2)
109
		(MSB )
110
		(LSB )
111
		(Type INPUT)
112
		(Location Left)
113
		(InputLoadLow -0.01)
114
		(InputLoadHigh 0.01)
115
		(OutputLoadLow )
116
		(OutputLoadHigh )
117
		(CheckLoad Both)
118
		(CheckIO Both)
119
		(CheckDir 1)
120
		(CheckAssert 1)
121
		(CheckOutput 1)
122
		(UnknownLoading 0)
123
		(PinShape Line)
124
		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
126
	)
127

  
128
	(Pin
129
		(Name IN1)
130
		(MSB )
131
		(LSB )
132
		(Type INPUT)
133
		(Location Left)
134
		(InputLoadLow -0.01)
135
		(InputLoadHigh 0.01)
136
		(OutputLoadLow )
137
		(OutputLoadHigh )
138
		(CheckLoad Both)
139
		(CheckIO Both)
140
		(CheckDir 1)
141
		(CheckAssert 1)
142
		(CheckOutput 1)
143
		(UnknownLoading 0)
144
		(PinShape Line)
145
		(DIFF_PAIR_PINS_POS )
146
		(DIFF_PAIR_PINS_NEG )
147
	)
148

  
149
	(Pin
150
		(Name NP1)
151
		(MSB )
152
		(LSB )
153
		(Type NC)
154
		(Location Left)
155
		(InputLoadLow )
156
		(InputLoadHigh )
157
		(OutputLoadLow )
158
		(OutputLoadHigh )
159
		(CheckLoad Off)
160
		(CheckIO Off)
161
		(CheckDir 0)
162
		(CheckAssert 0)
163
		(CheckOutput 0)
164
		(UnknownLoading 0)
165
		(PinShape Line)
166
		(DIFF_PAIR_PINS_POS )
167
		(DIFF_PAIR_PINS_NEG )
168
	)
169

  
170

  
171
)
trunk/librairies/polytech_ge_beta/tda2822m/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge_beta/tda2822m/metadata/revision.dat
1
(Cell	tda2822m
2

  
3
	(RevisionInfoBlock	
4

  
5
		(Baselined	0)
6

  
7
		(Revision	0.0.8)
8

  
9
		(ModificationStatus	NULL)
10

  
11
		(Status	Created)
12

  
13
		(ErrorStatus	0)
14

  
15
		(CreateInfo	
16

  
17
			(Time	09/21/11,16:17:03)
18

  
19
			(User	mforner)
20

  
21
			(Path	_polytech_ge_beta.tda2822m)
22

  
23
		)
24

  
25
		(LastModifyInfo	
26

  
27
			(Time	09/21/11,16:38:59)
28

  
29
			(User	mforner)
30

  
31
			(Path	_polytech_ge_beta.tda2822m)
32

  
33
		)
34

  
35
	)
36

  
37
	(Views	
38

  
39
		(View	Symbol
40

  
41
			(Symbols	1
42

  
43
				(Symbol	sym_1
44

  
45
					(Symbol_Type	Normal)
46

  
47
					(Max_Size	0)
48

  
49
					(Checksum	000000006307c98b)
50

  
51
					(RevisionInfoBlock	
52

  
53
						(Baselined	0)
54

  
55
						(Revision	0.0.8)
56

  
57
						(ModificationStatus	NULL)
58

  
59
						(Status	Created)
60

  
61
						(ErrorStatus	0)
62

  
63
						(CreateInfo	
64

  
65
							(Time	09/21/11,16:32:27)
66

  
67
							(User	mforner)
68

  
69
							(Path	_polytech_ge_beta.tda2822m)
70

  
71
						)
72

  
73
					)
74

  
75
				)
76

  
77
			)
78

  
79
			(Checksum	000000001b210387)
80

  
81
		)
82

  
83
		(View	Chips
84

  
85
			(Checksum	00000000900528c9)
86

  
87
			(Primitives	1
88

  
89
				(Primitive	TDA2822M
90

  
91
					(RevisionInfoBlock	
92

  
93
						(Baselined	0)
94

  
95
						(Revision	0.0.1)
96

  
97
						(ModificationStatus	NULL)
98

  
99
						(Status	Created)
100

  
101
						(ErrorStatus	0)
102

  
103
						(CreateInfo	
104

  
105
							(Time	09/21/11,16:17:40)
106

  
107
							(User	mforner)
108

  
109
							(Path	_polytech_ge_beta.tda2822m)
110

  
111
						)
112

  
113
					)
114

  
115
					(LogicalPhysicalPartRelation	
116

  
117
						(LogicalPart	TDA2822M
118

  
119
							(PackType	TDA2822M)
120

  
121
						)
122

  
123
					)
124

  
125
					(Packages	1
126

  
127
						(FunctionGroups	1
128

  
129
							(FunctionGroup	1[1]
130

  
131
								(Linkages	
132

  
133
									(Linkage	Symbol
134

  
135
										(Name	sym_1)
136

  
137
									)
138

  
139
								)
140

  
141
							)
142

  
143
						)
144

  
145
						(Linkages	
146

  
147
							(DefaultFootPrint	
148

  
149
								(Name	dip8_3)
150

  
151
							)
152

  
153
						)
154

  
155
					)
156

  
157
				)
158

  
159
			)
160

  
161
		)
162

  
163
		(Checksum	000000001d4b03a6)
164

  
165
	)
166

  
167
	(VersionInfoBlock	
168

  
169
		(ToolName	PDV)
170

  
171
		(Version	16.01-s021 (v16-1-53AR))
172

  
173
		(License	PCB_librarian_expert)
174

  
175
	)
176

  
177
	(Checksum	000000001c8703a6)
178

  
179
)
180

  
trunk/librairies/polytech_ge_beta/tda2822m/cfg_verilog/master.tag
1
expand.cfg
trunk/librairies/polytech_ge_beta/tda2822m/cfg_verilog/expand.cfg
1
config tda2822m;
2
design _polytech_ge_beta.tda2822m:sim_sch_1;
3
liblist standard, _polytech_ge, _polytech_ge_beta, rf_comp_lib;
4
viewlist vlog_map, hw_map, swift_map, vlog_model, hw_model, swift_model, vlog_structural, vlog_rtl, vlog_behavioral, vlog_system, mcvlog, pic_1, picopt_1, tbl_1, sim_sch_1, sch_1, entity;
5
stoplist vlog_model, swift_model;
6
endconfig
trunk/librairies/polytech_ge_beta/tda2822m/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge_beta/tda2822m/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'TDA2822M';
3
  pin
4
    'OUT1':
5
      PIN_NUMBER='(1)';
6
      OUTPUT_LOAD='(1.0,-1.0)';
7
    'VCC':
8
      PIN_NUMBER='(2)';
9
      PINUSE='POWER';
10
      NO_LOAD_CHECK='Both';
11
      NO_IO_CHECK='Both';
12
      NO_ASSERT_CHECK='TRUE';
13
      NO_DIR_CHECK='TRUE';
14
      ALLOW_CONNECT='TRUE';
15
    'OUT2':
16
      PIN_NUMBER='(3)';
17
      OUTPUT_LOAD='(1.0,-1.0)';
18
    'GND':
19
      PIN_NUMBER='(4)';
20
      PINUSE='GROUND';
21
      NO_LOAD_CHECK='Both';
22
      NO_IO_CHECK='Both';
23
      NO_ASSERT_CHECK='TRUE';
24
      NO_DIR_CHECK='TRUE';
25
      ALLOW_CONNECT='TRUE';
26
    'NP2':
27
      PIN_NUMBER='(5)';
28
      PINUSE='NC';
29
      NO_LOAD_CHECK='Both';
30
      NO_IO_CHECK='Both';
31
      NO_ASSERT_CHECK='TRUE';
32
      NO_DIR_CHECK='TRUE';
33
      ALLOW_CONNECT='TRUE';
34
    'IN2':
35
      PIN_NUMBER='(6)';
36
      INPUT_LOAD='(-0.01,0.01)';
37
    'IN1':
38
      PIN_NUMBER='(7)';
39
      INPUT_LOAD='(-0.01,0.01)';
40
    'NP1':
41
      PIN_NUMBER='(8)';
42
      PINUSE='NC';
43
      NO_LOAD_CHECK='Both';
44
      NO_IO_CHECK='Both';
45
      NO_ASSERT_CHECK='TRUE';
46
      NO_DIR_CHECK='TRUE';
47
      ALLOW_CONNECT='TRUE';
48
  end_pin;
49
  body
50
    PART_NAME='TDA2822M';
51
    BODY_NAME='TDA2822M';
52
    JEDEC_TYPE='dip8_3';
53
    PHYS_DES_PREFIX='U';
54
    CLASS='IC';
55
  end_body;
56
end_primitive;
57

  
58
END.
trunk/librairies/polytech_ge_beta/tda2822m/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge_beta/tda2822m/sym_1/symbol.css
1
P "CDS_LMAN_SYM_OUTLINE" "-125,125,125,-125" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
2
L -125 125 -125 -125 -1 0
3
L -125 125 125 125 -1 0
4
L 125 125 125 -125 -1 0
5
L -125 -125 125 -125 -1 0
6
T 22 -25 0 0 23 0 0 1 0 8 0
7
tda2822m
8
L 175 50 125 50 -1 0
9
C 175 50 "OUT1" 200 50 0 1 29 0 L
10
X "PIN_TEXT" "OUT1" 115 50 0 0 16 0 0 2 0 0 1 0 0
11
L 0 175 0 125 -1 0
12
C 0 175 "VCC" 0 200 0 1 29 1 L
13
X "PIN_TEXT" "Vcc" 25 100 0 0 17 0 0 2 0 0 1 0 0
14
L 175 -100 125 -100 -1 0
15
C 175 -100 "OUT2" 200 -99 0 1 29 0 L
16
X "PIN_TEXT" "OUT2" 117 -100 0 0 16 0 0 2 0 0 1 0 0
17
L -100 -175 -100 -125 -1 0
18
C -100 -175 "GND" -100 -200 0 1 29 1 R
19
X "PIN_TEXT" "GND" -86 -125 90 0 16 0 0 0 0 0 1 0 0
20
L -175 100 -125 100 -1 0
21
C -175 100 "NP2" -200 100 0 1 29 0 R
22
X "PIN_TEXT" "NP2" -100 100 0 0 16 0 0 0 0 0 1 0 0
23
L -175 50 -125 50 -1 0
24
C -175 50 "IN2" -200 50 0 1 29 0 R
25
X "PIN_TEXT" "IN2" -100 50 0 0 16 0 0 0 0 0 1 0 0
26
L -175 0 -125 0 -1 0
27
C -175 0 "IN1" -200 0 0 1 29 0 R
28
X "PIN_TEXT" "IN1" -100 0 0 0 16 0 0 0 0 0 1 0 0
29
L -175 -50 -125 -50 -1 0
30
C -175 -50 "NP1" -200 -50 0 1 29 0 R
31
X "PIN_TEXT" "NP1" -100 -50 0 0 16 0 0 0 0 0 1 0 0
32

  
33

  
trunk/librairies/polytech_ge_beta/tda2822m/cfg_package/master.tag
1
expand.cfg
trunk/librairies/polytech_ge_beta/tda2822m/cfg_package/expand.cfg
1
config tda2822m;
2
design _polytech_ge_beta.tda2822m:sch_1;
3
liblist standard, _polytech_ge, _polytech_ge_beta, rf_comp_lib;
4
viewlist chips, pic_1, picopt_1, sch_1, schematic, entity, functional;
5
stoplist chips;
6
endconfig
trunk/librairies/polytech_ge_beta/tda2822m/cfg_pic/master.tag
1
expand.cfg
trunk/librairies/polytech_ge_beta/tda2822m/cfg_pic/expand.cfg
1
config tda2822m;
2
design _polytech_ge_beta.tda2822m:sch_1;
3
liblist standard, _polytech_ge, _polytech_ge_beta, rf_comp_lib;
4
viewlist edif, vlog_rtl, vhdl_rtl, sch_1, entity;
5
stoplist none;
6
endconfig
trunk/librairies/polytech_ge_beta/tda2822m/psp_sim_1/master.tag
1
tda2822m.net
trunk/librairies/polytech_ge_beta/tda2822m/psp_sim_1/tda2822m.opj
1
(ExpressProject  tda2822m
2
)
trunk/librairies/polytech_ge_beta/tda2822m/cfg_vhdl/master.tag
1
expand.cfg
trunk/librairies/polytech_ge_beta/tda2822m/cfg_vhdl/expand.cfg
1
config tda2822m;
2
design _polytech_ge_beta.tda2822m:sim_sch_1;
3
liblist standard, _polytech_ge, _polytech_ge_beta, rf_comp_lib;
4
viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl_system, mc_arch, pic_1, picopt_1, sim_sch_1, sch_1;
5
stoplist none;
6
endconfig
trunk/librairies/polytech_ge_beta/tda2822m/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge_beta/tda2822m/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 21, 2011  17:08:27
trunk/librairies/polytech_ge_beta/tda2822m/entity/verilog.v
1
// generated by newgenasym  Wed Sep 21 17:08:27 2011
2

  
3

  
4
module tda2822m (gnd, in1, in2, np1, np2, out1, out2, vcc);
5
    input gnd;
6
    input in1;
7
    input in2;
8
    inout np1;
9
    inout np2;
10
    output out1;
11
    output out2;
12
    input vcc;
13

  
14

  
15
    initial
16
        begin
17
        end
18

  
19
endmodule
trunk/librairies/polytech_ge_beta/tda2822m/entity/vhdl.vhd
1
-- generated by newgenasym Wed Sep 21 17:08:27 2011
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity tda2822m is
7
    port (    
8
	GND:       IN     STD_LOGIC;    
9
	IN1:       IN     STD_LOGIC;    
10
	IN2:       IN     STD_LOGIC;    
11
	NP1:       INOUT  STD_LOGIC;    
12
	NP2:       INOUT  STD_LOGIC;    
13
	OUT1:      OUT    STD_LOGIC;    
14
	OUT2:      OUT    STD_LOGIC;    
15
	VCC:       IN     STD_LOGIC);
16
end tda2822m;
trunk/librairies/polytech_ge_beta/tda2822m/sch_1/module_order.dat
1
Version 15.0
2
START_MODULEORDER
3
END_MODULEORDER

Also available in: Unified diff