Revision 261

View differences:

trunk/librairies/polytech_ge_beta/mcp4901/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name VDD)
4
		(MSB )
5
		(LSB )
6
		(Type ANALOG)
7
		(Location Left)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape Line)
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name CS)
25
		(MSB )
26
		(LSB )
27
		(Type ANALOG)
28
		(Location Left)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow )
32
		(OutputLoadHigh )
33
		(CheckLoad Off)
34
		(CheckIO Off)
35
		(CheckDir 0)
36
		(CheckAssert 0)
37
		(CheckOutput 0)
38
		(UnknownLoading 0)
39
		(PinShape Line)
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name SCK)
46
		(MSB )
47
		(LSB )
48
		(Type ANALOG)
49
		(Location Left)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow )
53
		(OutputLoadHigh )
54
		(CheckLoad Off)
55
		(CheckIO Off)
56
		(CheckDir 0)
57
		(CheckAssert 0)
58
		(CheckOutput 0)
59
		(UnknownLoading 0)
60
		(PinShape Line)
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name SDI)
67
		(MSB )
68
		(LSB )
69
		(Type ANALOG)
70
		(Location Left)
71
		(InputLoadLow )
72
		(InputLoadHigh )
73
		(OutputLoadLow )
74
		(OutputLoadHigh )
75
		(CheckLoad Off)
76
		(CheckIO Off)
77
		(CheckDir 0)
78
		(CheckAssert 0)
79
		(CheckOutput 0)
80
		(UnknownLoading 0)
81
		(PinShape Line)
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name LDAC)
88
		(MSB )
89
		(LSB )
90
		(Type ANALOG)
91
		(Location Right)
92
		(InputLoadLow )
93
		(InputLoadHigh )
94
		(OutputLoadLow )
95
		(OutputLoadHigh )
96
		(CheckLoad Off)
97
		(CheckIO Off)
98
		(CheckDir 0)
99
		(CheckAssert 0)
100
		(CheckOutput 0)
101
		(UnknownLoading 0)
102
		(PinShape Line)
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name VREF)
109
		(MSB )
110
		(LSB )
111
		(Type ANALOG)
112
		(Location Right)
113
		(InputLoadLow )
114
		(InputLoadHigh )
115
		(OutputLoadLow )
116
		(OutputLoadHigh )
117
		(CheckLoad Off)
118
		(CheckIO Off)
119
		(CheckDir 0)
120
		(CheckAssert 0)
121
		(CheckOutput 0)
122
		(UnknownLoading 0)
123
		(PinShape Line)
124
		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
126
	)
127

  
128
	(Pin
129
		(Name VSS)
130
		(MSB )
131
		(LSB )
132
		(Type ANALOG)
133
		(Location Right)
134
		(InputLoadLow )
135
		(InputLoadHigh )
136
		(OutputLoadLow )
137
		(OutputLoadHigh )
138
		(CheckLoad Off)
139
		(CheckIO Off)
140
		(CheckDir 0)
141
		(CheckAssert 0)
142
		(CheckOutput 0)
143
		(UnknownLoading 0)
144
		(PinShape Line)
145
		(DIFF_PAIR_PINS_POS )
146
		(DIFF_PAIR_PINS_NEG )
147
	)
148

  
149
	(Pin
150
		(Name VOUT)
151
		(MSB )
152
		(LSB )
153
		(Type ANALOG)
154
		(Location Right)
155
		(InputLoadLow )
156
		(InputLoadHigh )
157
		(OutputLoadLow )
158
		(OutputLoadHigh )
159
		(CheckLoad Off)
160
		(CheckIO Off)
161
		(CheckDir 0)
162
		(CheckAssert 0)
163
		(CheckOutput 0)
164
		(UnknownLoading 0)
165
		(PinShape Line)
166
		(DIFF_PAIR_PINS_POS )
167
		(DIFF_PAIR_PINS_NEG )
168
	)
169

  
170

  
171
)
trunk/librairies/polytech_ge_beta/mcp4901/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge_beta/mcp4901/metadata/revision.dat
1
(Cell	mcp4901
2

  
3
	(RevisionInfoBlock	
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5
		(Baselined	0)
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		(Revision	0.0.3)
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		(ModificationStatus	NULL)
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11
		(Status	Created)
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13
		(ErrorStatus	0)
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15
		(CreateInfo	
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17
			(Time	05/31/11,14:51:06)
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			(User	profs)
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			(Path	_polytech_ge_beta.mcp4901)
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		)
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		(LastModifyInfo	
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			(Time	05/31/11,15:11:59)
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			(User	profs)
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			(Path	_polytech_ge_beta.mcp4901)
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		)
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	)
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	(Views	
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		(View	Symbol
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			(Symbols	2
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				(Symbol	sym_2
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					(Symbol_Type	Normal)
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					(Max_Size	0)
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					(Checksum	0000000039bec6e1)
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.1)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	05/31/11,15:11:44)
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							(User	profs)
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							(Path	_polytech_ge_beta.mcp4901)
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						)
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					)
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				)
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				(Symbol	sym_1
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					(Symbol_Type	Normal)
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					(Max_Size	0)
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					(Checksum	00000000c398da36)
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.2)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	05/31/11,15:06:30)
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							(User	profs)
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							(Path	_polytech_ge_beta.mcp4901)
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						)
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					)
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				)
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			)
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			(Checksum	000000001dbd03b1)
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		)
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		(View	Chips
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			(Checksum	00000000afc7b125)
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			(Primitives	1
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				(Primitive	MCP4901
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.2)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	05/31/11,14:51:50)
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							(User	profs)
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							(Path	_polytech_ge_beta.mcp4901)
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						)
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					)
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	MCP4901
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							(PackType	MCP4901)
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						)
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					)
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					(Packages	1
160

  
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						(FunctionGroups	1
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							(FunctionGroup	1[1]
164

  
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								(Linkages	
166

  
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									(Linkage	Symbol
168

  
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										(Name	sym_2)
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									)
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									(Linkage	Symbol
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										(Name	sym_1)
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									)
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								)
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							)
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						)
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	dip8_3)
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							)
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						)
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					)
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				)
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			)
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		)
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		(Checksum	000000001e1a03e4)
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	)
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	(VersionInfoBlock	
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		(ToolName	PDV)
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		(Version	16.01-s021 (v16-1-53AR))
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		(License	PCB_librarian_expert)
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	)
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	(Checksum	000000001c7d03a5)
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)
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trunk/librairies/polytech_ge_beta/mcp4901/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge_beta/mcp4901/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'MCP4901';
3
  pin
4
    'VDD':
5
      PIN_NUMBER='(1)';
6
      PIN_TYPE='ANALOG';
7
      NO_LOAD_CHECK='Both';
8
      NO_IO_CHECK='Both';
9
      NO_ASSERT_CHECK='TRUE';
10
      NO_DIR_CHECK='TRUE';
11
      ALLOW_CONNECT='TRUE';
12
    'CS':
13
      PIN_NUMBER='(2)';
14
      PIN_TYPE='ANALOG';
15
      NO_LOAD_CHECK='Both';
16
      NO_IO_CHECK='Both';
17
      NO_ASSERT_CHECK='TRUE';
18
      NO_DIR_CHECK='TRUE';
19
      ALLOW_CONNECT='TRUE';
20
    'SCK':
21
      PIN_NUMBER='(3)';
22
      PIN_TYPE='ANALOG';
23
      NO_LOAD_CHECK='Both';
24
      NO_IO_CHECK='Both';
25
      NO_ASSERT_CHECK='TRUE';
26
      NO_DIR_CHECK='TRUE';
27
      ALLOW_CONNECT='TRUE';
28
    'SDI':
29
      PIN_NUMBER='(4)';
30
      PIN_TYPE='ANALOG';
31
      NO_LOAD_CHECK='Both';
32
      NO_IO_CHECK='Both';
33
      NO_ASSERT_CHECK='TRUE';
34
      NO_DIR_CHECK='TRUE';
35
      ALLOW_CONNECT='TRUE';
36
    'LDAC':
37
      PIN_NUMBER='(5)';
38
      PIN_TYPE='ANALOG';
39
      NO_LOAD_CHECK='Both';
40
      NO_IO_CHECK='Both';
41
      NO_ASSERT_CHECK='TRUE';
42
      NO_DIR_CHECK='TRUE';
43
      ALLOW_CONNECT='TRUE';
44
    'VREF':
45
      PIN_NUMBER='(6)';
46
      PIN_TYPE='ANALOG';
47
      NO_LOAD_CHECK='Both';
48
      NO_IO_CHECK='Both';
49
      NO_ASSERT_CHECK='TRUE';
50
      NO_DIR_CHECK='TRUE';
51
      ALLOW_CONNECT='TRUE';
52
    'VSS':
53
      PIN_NUMBER='(7)';
54
      PIN_TYPE='ANALOG';
55
      NO_LOAD_CHECK='Both';
56
      NO_IO_CHECK='Both';
57
      NO_ASSERT_CHECK='TRUE';
58
      NO_DIR_CHECK='TRUE';
59
      ALLOW_CONNECT='TRUE';
60
    'VOUT':
61
      PIN_NUMBER='(8)';
62
      PIN_TYPE='ANALOG';
63
      NO_LOAD_CHECK='Both';
64
      NO_IO_CHECK='Both';
65
      NO_ASSERT_CHECK='TRUE';
66
      NO_DIR_CHECK='TRUE';
67
      ALLOW_CONNECT='TRUE';
68
  end_pin;
69
  body
70
    PART_NAME='MCP4901';
71
    BODY_NAME='MCP4901';
72
    JEDEC_TYPE='dip8_3';
73
    PHYS_DES_PREFIX='U';
74
    CLASS='IC';
75
  end_body;
76
end_primitive;
77

  
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END.
trunk/librairies/polytech_ge_beta/mcp4901/sym_1/master.tag
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symbol.css
trunk/librairies/polytech_ge_beta/mcp4901/sym_1/symbol.css
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trunk/librairies/polytech_ge_beta/mcp4901/sym_2/master.tag
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trunk/librairies/polytech_ge_beta/mcp4901/sym_2/symbol.css
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trunk/librairies/polytech_ge_beta/mcp4901/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge_beta/mcp4901/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on May 31, 2011  15:22:26
trunk/librairies/polytech_ge_beta/mcp4901/entity/verilog.v
1
// generated by newgenasym  Tue May 31 15:22:25 2011
2

  
3

  
4
module mcp4901 (cs, ldac, sck, sdi, vdd, vout, vref, vss);
5
    inout cs;
6
    inout ldac;
7
    inout sck;
8
    inout sdi;
9
    inout vdd;
10
    inout vout;
11
    inout vref;
12
    inout vss;
13

  
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15
    initial
16
        begin
17
        end
18

  
19
endmodule
trunk/librairies/polytech_ge_beta/mcp4901/entity/vhdl.vhd
1
-- generated by newgenasym Tue May 31 15:22:25 2011
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity mcp4901 is
7
    port (    
8
	CS:        INOUT  STD_LOGIC;    
9
	LDAC:      INOUT  STD_LOGIC;    
10
	SCK:       INOUT  STD_LOGIC;    
11
	SDI:       INOUT  STD_LOGIC;    
12
	VDD:       INOUT  STD_LOGIC;    
13
	VOUT:      INOUT  STD_LOGIC;    
14
	VREF:      INOUT  STD_LOGIC;    
15
	VSS:       INOUT  STD_LOGIC);
16
end mcp4901;

Also available in: Unified diff