Revision 260

View differences:

trunk/librairies/polytech_ge/bp/chips/chips.prt
1 1
FILE_TYPE=LIBRARY_PARTS;
2 2
primitive 'BP_THRU';
3 3
  pin
4
    '1':
5
      PIN_NUMBER='(1)';
4
    '2':
5
      PIN_NUMBER='(3)';
6 6
      PIN_TYPE='ANALOG';
7
      PIN_GROUP='0';
7 8
      NO_LOAD_CHECK='Both';
8 9
      NO_IO_CHECK='Both';
9 10
      ALLOW_CONNECT='TRUE';
10
    '2':
11
      PIN_NUMBER='(3)';
11
    '1':
12
      PIN_NUMBER='(1)';
12 13
      PIN_TYPE='ANALOG';
14
      PIN_GROUP='0';
13 15
      NO_LOAD_CHECK='Both';
14 16
      NO_IO_CHECK='Both';
15 17
      ALLOW_CONNECT='TRUE';
trunk/librairies/polytech_ge/bp/entity/master.tag
1
vhdl.vhd
2 1
verilog.v
trunk/librairies/polytech_ge/bp/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Apr 11, 2008  10:51:33
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on May 31, 2011  14:19:30
trunk/librairies/polytech_ge/bp/entity/verilog.v
1
// generated by newgenasym  Wed Nov 24 09:24:37 2010
1
// generated by newgenasym  Tue May 31 14:19:30 2011
2 2

  
3 3

  
4 4
module bp (\1 , \2 );
trunk/librairies/polytech_ge/bp/entity/vhdl.vhd
1
-- generated by newgenasym Wed Nov 24 09:24:37 2010
1
-- generated by newgenasym Tue May 31 14:19:30 2011
2 2

  
3 3
library ieee;
4 4
use     ieee.std_logic_1164.all;
5 5
use     work.all;
6
entity BP is
6
entity bp is
7 7
    port (    
8 8
	\1\:       INOUT  STD_LOGIC;    
9 9
	\2\:       INOUT  STD_LOGIC);
10
end BP;
10
end bp;

Also available in: Unified diff