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psd-data / trunk / librairies / polytech_ge_beta / trans1 / entity / vhdl.vhd @ 26

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-- generated by newgenasym Thu Sep 16 09:17:14 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity TRANS1 is
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    port (    
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	N:         IN     STD_LOGIC;    
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	P:         IN     STD_LOGIC;    
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	S1N:       OUT    STD_LOGIC;    
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	S1P:       OUT    STD_LOGIC;    
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	S2N:       OUT    STD_LOGIC;    
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	S2P:       OUT    STD_LOGIC);
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end TRANS1;