Statistics
| Revision:

psd-data / trunk / librairies / polytech_ge_beta / trans1 / entity / verilog.v @ 26

History | View | Annotate | Download (238 Bytes)

1
// generated by newgenasym  Thu Sep 16 09:17:14 2010
2

    
3

    
4
module trans1 (n, p, s1n, s1p, s2n, s2p);
5
    input n;
6
    input p;
7
    output s1n;
8
    output s1p;
9
    output s2n;
10
    output s2p;
11

    
12

    
13
    initial
14
        begin
15
        end
16

    
17
endmodule