Revision 252

View differences:

trunk/librairies/polytech_ge/transfo_2_2_sym/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name SN2)
4
		(MSB )
5
		(LSB )
6
		(Type ANALOG)
7
		(Location Left)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape )
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name SP1)
25
		(MSB )
26
		(LSB )
27
		(Type ANALOG)
28
		(Location Left)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow )
32
		(OutputLoadHigh )
33
		(CheckLoad Off)
34
		(CheckIO Off)
35
		(CheckDir 0)
36
		(CheckAssert 0)
37
		(CheckOutput 0)
38
		(UnknownLoading 0)
39
		(PinShape )
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name P1)
46
		(MSB )
47
		(LSB )
48
		(Type ANALOG)
49
		(Location Left)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow )
53
		(OutputLoadHigh )
54
		(CheckLoad Off)
55
		(CheckIO Off)
56
		(CheckDir 0)
57
		(CheckAssert 0)
58
		(CheckOutput 0)
59
		(UnknownLoading 0)
60
		(PinShape )
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name N1)
67
		(MSB )
68
		(LSB )
69
		(Type ANALOG)
70
		(Location Left)
71
		(InputLoadLow )
72
		(InputLoadHigh )
73
		(OutputLoadLow )
74
		(OutputLoadHigh )
75
		(CheckLoad Off)
76
		(CheckIO Off)
77
		(CheckDir 0)
78
		(CheckAssert 0)
79
		(CheckOutput 0)
80
		(UnknownLoading 0)
81
		(PinShape )
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name N2)
88
		(MSB )
89
		(LSB )
90
		(Type ANALOG)
91
		(Location Left)
92
		(InputLoadLow )
93
		(InputLoadHigh )
94
		(OutputLoadLow )
95
		(OutputLoadHigh )
96
		(CheckLoad Off)
97
		(CheckIO Off)
98
		(CheckDir 0)
99
		(CheckAssert 0)
100
		(CheckOutput 0)
101
		(UnknownLoading 0)
102
		(PinShape )
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name SN1)
109
		(MSB )
110
		(LSB )
111
		(Type ANALOG)
112
		(Location Left)
113
		(InputLoadLow )
114
		(InputLoadHigh )
115
		(OutputLoadLow )
116
		(OutputLoadHigh )
117
		(CheckLoad Off)
118
		(CheckIO Off)
119
		(CheckDir 0)
120
		(CheckAssert 0)
121
		(CheckOutput 0)
122
		(UnknownLoading 0)
123
		(PinShape )
124
		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
126
	)
127

  
128
	(Pin
129
		(Name SP2)
130
		(MSB )
131
		(LSB )
132
		(Type ANALOG)
133
		(Location Left)
134
		(InputLoadLow )
135
		(InputLoadHigh )
136
		(OutputLoadLow )
137
		(OutputLoadHigh )
138
		(CheckLoad Off)
139
		(CheckIO Off)
140
		(CheckDir 0)
141
		(CheckAssert 0)
142
		(CheckOutput 0)
143
		(UnknownLoading 0)
144
		(PinShape )
145
		(DIFF_PAIR_PINS_POS )
146
		(DIFF_PAIR_PINS_NEG )
147
	)
148

  
149
	(Pin
150
		(Name P2)
151
		(MSB )
152
		(LSB )
153
		(Type ANALOG)
154
		(Location Left)
155
		(InputLoadLow )
156
		(InputLoadHigh )
157
		(OutputLoadLow )
158
		(OutputLoadHigh )
159
		(CheckLoad Off)
160
		(CheckIO Off)
161
		(CheckDir 0)
162
		(CheckAssert 0)
163
		(CheckOutput 0)
164
		(UnknownLoading 0)
165
		(PinShape )
166
		(DIFF_PAIR_PINS_POS )
167
		(DIFF_PAIR_PINS_NEG )
168
	)
169

  
170

  
171
)
trunk/librairies/polytech_ge/transfo_2_2_sym/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge/transfo_2_2_sym/metadata/revision.dat
1
(Cell	transfo_2_2_sym
2

  
3
	(RevisionInfoBlock	
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		(Baselined	0)
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		(Revision	0.0.1)
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		(ModificationStatus	NULL)
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11
		(Status	Created)
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13
		(ErrorStatus	0)
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15
		(CreateInfo	
16

  
17
			(Time	05/24/11,17:23:35)
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			(User	profs)
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			(Path	_polytech_ge.transfo_2_2_sym)
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		)
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		(LastModifyInfo	
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			(Time	10/06/10,17:23:45)
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			(User	profs)
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			(Path	_polytech_ge.transformateur_2_2_sym)
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		)
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	)
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	(Views	
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		(View	Symbol
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			(Symbols	1
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				(Symbol	sym_1
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					(Symbol_Type	Normal)
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					(Max_Size	0)
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					(Checksum	00000000b334b067)
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.1)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	05/24/11,17:23:35)
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							(User	profs)
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							(Path	_polytech_ge.transfo_2_2_sym)
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						)
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					)
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				)
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			)
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			(Checksum	000000001c36037c)
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		)
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		(View	Chips
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			(Checksum	00000000d46fbec7)
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			(Primitives	2
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89
				(Primitive	transfo_2_2_sym_TES_1064
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.1)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	05/24/11,17:23:35)
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							(User	profs)
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							(Path	_polytech_ge.transfo_2_2_sym)
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						)
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					)
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	transfo_2_2_sym
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							(PackType	transfo_2_2_sym_TES_1064)
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					(Packages	1
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						(FunctionGroups	1
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							(FunctionGroup	1[1]
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								(Linkages	
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									(Linkage	Symbol
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										(Name	sym_1)
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									)
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								)
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							)
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						)
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	transfo_tes1064_2x110v_2x15v)
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							)
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						)
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					)
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				)
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				(Primitive	transfo_2_2_sym_TES_165
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.1)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	05/24/11,17:23:35)
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							(User	profs)
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							(Path	_polytech_ge.transfo_2_2_sym)
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						)
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					)
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	transfo_2_2_sym
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							(PackType	transfo_2_2_sym_TES_165)
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						)
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					)
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					(Packages	1
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						(FunctionGroups	1
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							(FunctionGroup	1[1]
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								(Linkages	
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									(Linkage	Symbol
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										(Name	sym_1)
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									)
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								)
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							)
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						)
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	tes_165)
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							)
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						)
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					)
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				)
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			)
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		)
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		(Checksum	000000001d5c03a9)
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	)
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	(VersionInfoBlock	
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		(ToolName	PDV)
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		(Version	16.01-s021 (v16-1-53AR))
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		(License	Concept_HDL_expert)
244

  
245
	)
246

  
247
	(Checksum	000000001c9503ab)
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249
)
250

  
trunk/librairies/polytech_ge/transfo_2_2_sym/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge/transfo_2_2_sym/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'TRANSFO_2_2_SYM_TES_1064';
3
  pin
4
    'P1':
5
      PIN_NUMBER='(1)';
6
      PIN_TYPE='ANALOG';
7
      PIN_GROUP='1';
8
      NO_LOAD_CHECK='Both';
9
      NO_IO_CHECK='Both';
10
      NO_ASSERT_CHECK='TRUE';
11
      NO_DIR_CHECK='TRUE';
12
      ALLOW_CONNECT='TRUE';
13
    'SP1':
14
      PIN_NUMBER='(5)';
15
      PIN_TYPE='ANALOG';
16
      PIN_GROUP='3';
17
      NO_LOAD_CHECK='Both';
18
      NO_IO_CHECK='Both';
19
      NO_ASSERT_CHECK='TRUE';
20
      NO_DIR_CHECK='TRUE';
21
      ALLOW_CONNECT='TRUE';
22
    'SP2':
23
      PIN_NUMBER='(7)';
24
      PIN_TYPE='ANALOG';
25
      PIN_GROUP='4';
26
      NO_LOAD_CHECK='Both';
27
      NO_IO_CHECK='Both';
28
      NO_ASSERT_CHECK='TRUE';
29
      NO_DIR_CHECK='TRUE';
30
      ALLOW_CONNECT='TRUE';
31
    'N1':
32
      PIN_NUMBER='(2)';
33
      PIN_TYPE='ANALOG';
34
      PIN_GROUP='1';
35
      NO_LOAD_CHECK='Both';
36
      NO_IO_CHECK='Both';
37
      NO_ASSERT_CHECK='TRUE';
38
      NO_DIR_CHECK='TRUE';
39
      ALLOW_CONNECT='TRUE';
40
    'N2':
41
      PIN_NUMBER='(4)';
42
      PIN_TYPE='ANALOG';
43
      PIN_GROUP='2';
44
      NO_LOAD_CHECK='Both';
45
      NO_IO_CHECK='Both';
46
      NO_ASSERT_CHECK='TRUE';
47
      NO_DIR_CHECK='TRUE';
48
      ALLOW_CONNECT='TRUE';
49
    'SN1':
50
      PIN_NUMBER='(6)';
51
      PIN_TYPE='ANALOG';
52
      PIN_GROUP='3';
53
      NO_LOAD_CHECK='Both';
54
      NO_IO_CHECK='Both';
55
      NO_ASSERT_CHECK='TRUE';
56
      NO_DIR_CHECK='TRUE';
57
      ALLOW_CONNECT='TRUE';
58
    'SN2':
59
      PIN_NUMBER='(8)';
60
      PIN_TYPE='ANALOG';
61
      PIN_GROUP='4';
62
      NO_LOAD_CHECK='Both';
63
      NO_IO_CHECK='Both';
64
      NO_ASSERT_CHECK='TRUE';
65
      NO_DIR_CHECK='TRUE';
66
      ALLOW_CONNECT='TRUE';
67
    'P2':
68
      PIN_NUMBER='(3)';
69
      PIN_TYPE='ANALOG';
70
      PIN_GROUP='2';
71
      NO_LOAD_CHECK='Both';
72
      NO_IO_CHECK='Both';
73
      NO_ASSERT_CHECK='TRUE';
74
      NO_DIR_CHECK='TRUE';
75
      ALLOW_CONNECT='TRUE';
76
  end_pin;
77
  body
78
    PART_NAME='transfo_2_2_sym';
79
    BODY_NAME='TRANSFO_2_2_SYM';
80
    JEDEC_TYPE='transfo_tes1064_2x110v_2x15v';
81
    PHYS_DES_PREFIX='U';
82
    CLASS='IC';
83
  end_body;
84
end_primitive;
85

  
86
primitive 'TRANSFO_2_2_SYM_TES_165';
87
  pin
88
    'SN2':
89
      PIN_NUMBER='(4)';
90
      PIN_TYPE='ANALOG';
91
      PIN_GROUP='4';
92
      NO_LOAD_CHECK='Both';
93
      NO_IO_CHECK='Both';
94
      NO_ASSERT_CHECK='TRUE';
95
      NO_DIR_CHECK='TRUE';
96
      ALLOW_CONNECT='TRUE';
97
    'SP1':
98
      PIN_NUMBER='(1)';
99
      PIN_TYPE='ANALOG';
100
      PIN_GROUP='3';
101
      NO_LOAD_CHECK='Both';
102
      NO_IO_CHECK='Both';
103
      NO_ASSERT_CHECK='TRUE';
104
      NO_DIR_CHECK='TRUE';
105
      ALLOW_CONNECT='TRUE';
106
    'P1':
107
      PIN_NUMBER='(5)';
108
      PIN_TYPE='ANALOG';
109
      PIN_GROUP='1';
110
      NO_LOAD_CHECK='Both';
111
      NO_IO_CHECK='Both';
112
      NO_ASSERT_CHECK='TRUE';
113
      NO_DIR_CHECK='TRUE';
114
      ALLOW_CONNECT='TRUE';
115
    'N1':
116
      PIN_NUMBER='(6)';
117
      PIN_TYPE='ANALOG';
118
      PIN_GROUP='1';
119
      NO_LOAD_CHECK='Both';
120
      NO_IO_CHECK='Both';
121
      NO_ASSERT_CHECK='TRUE';
122
      NO_DIR_CHECK='TRUE';
123
      ALLOW_CONNECT='TRUE';
124
    'N2':
125
      PIN_NUMBER='(8)';
126
      PIN_TYPE='ANALOG';
127
      PIN_GROUP='2';
128
      NO_LOAD_CHECK='Both';
129
      NO_IO_CHECK='Both';
130
      NO_ASSERT_CHECK='TRUE';
131
      NO_DIR_CHECK='TRUE';
132
      ALLOW_CONNECT='TRUE';
133
    'SN1':
134
      PIN_NUMBER='(2)';
135
      PIN_TYPE='ANALOG';
136
      PIN_GROUP='3';
137
      NO_LOAD_CHECK='Both';
138
      NO_IO_CHECK='Both';
139
      NO_ASSERT_CHECK='TRUE';
140
      NO_DIR_CHECK='TRUE';
141
      ALLOW_CONNECT='TRUE';
142
    'SP2':
143
      PIN_NUMBER='(3)';
144
      PIN_TYPE='ANALOG';
145
      PIN_GROUP='4';
146
      NO_LOAD_CHECK='Both';
147
      NO_IO_CHECK='Both';
148
      NO_ASSERT_CHECK='TRUE';
149
      NO_DIR_CHECK='TRUE';
150
      ALLOW_CONNECT='TRUE';
151
    'P2':
152
      PIN_NUMBER='(7)';
153
      PIN_TYPE='ANALOG';
154
      PIN_GROUP='2';
155
      NO_LOAD_CHECK='Both';
156
      NO_IO_CHECK='Both';
157
      NO_ASSERT_CHECK='TRUE';
158
      NO_DIR_CHECK='TRUE';
159
      ALLOW_CONNECT='TRUE';
160
  end_pin;
161
  body
162
    PART_NAME='transfo_2_2_sym';
163
    BODY_NAME='TRANSFO_2_2_SYM';
164
    JEDEC_TYPE='tes_165';
165
    PHYS_DES_PREFIX='U';
166
    CLASS='IC';
167
  end_body;
168
end_primitive;
169

  
170
END.
trunk/librairies/polytech_ge/transfo_2_2_sym/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge/transfo_2_2_sym/sym_1/symbol.css
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P "CDS_LMAN_SYM_OUTLINE" "-100,300,150,-250" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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L -100 -250 150 -250 -1 0
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L -100 300 150 300 -1 0
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A -50 -25 25 270 450 16
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A -50 -75 25 270 450 16
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A 100 -75 25 90 270 16
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A -50 -175 25 270 450 16
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A -50 75 25 270 450 16
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A -50 175 25 270 450 16
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A 100 175 25 90 270 16
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A -50 -125 25 270 450 16
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A 100 125 25 90 270 16
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A -50 125 25 270 450 16
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A -50 225 25 270 450 16
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P "PACK_TYPE" "TES_1064" -100 -296 0 0 29 0 0 0 0 0 1 0 0
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L 200 -150 100 -150 -1 0
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C 200 -150 "SN2" 225 -150 0 1 29 0 L
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L 200 200 100 200 -1 0
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C 200 200 "SP1" 225 200 0 1 29 0 L
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L -150 250 -50 250 -1 0
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C -150 250 "P1" -175 250 0 1 29 0 R
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L -150 50 -50 50 -1 0
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C -150 50 "N1" -175 50 0 1 29 0 R
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L -150 -200 -50 -200 -1 0
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C -150 -200 "N2" -175 -200 0 1 29 0 R
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L 200 100 100 100 -1 0
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C 200 100 "SN1" 225 100 0 1 29 0 L
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L 200 -50 100 -50 -1 0
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C 200 -50 "SP2" 225 -50 0 1 29 0 L
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L -150 0 -50 0 -1 0
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C -150 0 "P2" -175 0 0 1 29 0 R
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36

  
trunk/librairies/polytech_ge/transfo_2_2_sym/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge/transfo_2_2_sym/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on May 24, 2011  17:23:36
trunk/librairies/polytech_ge/transfo_2_2_sym/entity/verilog.v
1
// generated by newgenasym  Tue May 24 17:23:36 2011
2

  
3

  
4
module transfo_2_2_sym (n1, n2, p1, p2, sn1, sn2, sp1, sp2);
5
    inout n1;
6
    inout n2;
7
    inout p1;
8
    inout p2;
9
    inout sn1;
10
    inout sn2;
11
    inout sp1;
12
    inout sp2;
13

  
14

  
15
    initial
16
        begin
17
        end
18

  
19
endmodule
trunk/librairies/polytech_ge/transfo_2_2_sym/entity/vhdl.vhd
1
-- generated by newgenasym Tue May 24 17:23:36 2011
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity transfo_2_2_sym is
7
    port (    
8
	N1:        INOUT  STD_LOGIC;    
9
	N2:        INOUT  STD_LOGIC;    
10
	P1:        INOUT  STD_LOGIC;    
11
	P2:        INOUT  STD_LOGIC;    
12
	SN1:       INOUT  STD_LOGIC;    
13
	SN2:       INOUT  STD_LOGIC;    
14
	SP1:       INOUT  STD_LOGIC;    
15
	SP2:       INOUT  STD_LOGIC);
16
end transfo_2_2_sym;

Also available in: Unified diff