Revision 250

View differences:

trunk/librairies/polytech_ge/transfo_1_2_sym/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name S1P)
4
		(MSB )
5
		(LSB )
6
		(Type UNSPEC)
7
		(Location Right)
8
		(InputLoadLow )
9
		(InputLoadHigh )
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Off)
13
		(CheckIO Off)
14
		(CheckDir 0)
15
		(CheckAssert 0)
16
		(CheckOutput 0)
17
		(UnknownLoading 0)
18
		(PinShape )
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name S2P)
25
		(MSB )
26
		(LSB )
27
		(Type UNSPEC)
28
		(Location Right)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow )
32
		(OutputLoadHigh )
33
		(CheckLoad Off)
34
		(CheckIO Off)
35
		(CheckDir 0)
36
		(CheckAssert 0)
37
		(CheckOutput 0)
38
		(UnknownLoading 0)
39
		(PinShape )
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name S2N)
46
		(MSB )
47
		(LSB )
48
		(Type UNSPEC)
49
		(Location Right)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow )
53
		(OutputLoadHigh )
54
		(CheckLoad Off)
55
		(CheckIO Off)
56
		(CheckDir 0)
57
		(CheckAssert 0)
58
		(CheckOutput 0)
59
		(UnknownLoading 0)
60
		(PinShape )
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name P)
67
		(MSB )
68
		(LSB )
69
		(Type ANALOG)
70
		(Location Left)
71
		(InputLoadLow )
72
		(InputLoadHigh )
73
		(OutputLoadLow )
74
		(OutputLoadHigh )
75
		(CheckLoad Off)
76
		(CheckIO Off)
77
		(CheckDir 0)
78
		(CheckAssert 0)
79
		(CheckOutput 0)
80
		(UnknownLoading 0)
81
		(PinShape )
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name N)
88
		(MSB )
89
		(LSB )
90
		(Type ANALOG)
91
		(Location Left)
92
		(InputLoadLow )
93
		(InputLoadHigh )
94
		(OutputLoadLow )
95
		(OutputLoadHigh )
96
		(CheckLoad Off)
97
		(CheckIO Off)
98
		(CheckDir 0)
99
		(CheckAssert 0)
100
		(CheckOutput 0)
101
		(UnknownLoading 0)
102
		(PinShape )
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107
	(Pin
108
		(Name S1N)
109
		(MSB )
110
		(LSB )
111
		(Type UNSPEC)
112
		(Location Right)
113
		(InputLoadLow )
114
		(InputLoadHigh )
115
		(OutputLoadLow )
116
		(OutputLoadHigh )
117
		(CheckLoad Off)
118
		(CheckIO Off)
119
		(CheckDir 0)
120
		(CheckAssert 0)
121
		(CheckOutput 0)
122
		(UnknownLoading 0)
123
		(PinShape )
124
		(DIFF_PAIR_PINS_POS )
125
		(DIFF_PAIR_PINS_NEG )
126
	)
127

  
128

  
129
)
trunk/librairies/polytech_ge/transfo_1_2_sym/metadata/master.tag
1
revision.dat
trunk/librairies/polytech_ge/transfo_1_2_sym/metadata/revision.dat
1
(Cell	transfo_1_2_sym
2

  
3
	(RevisionInfoBlock	
4

  
5
		(Baselined	0)
6

  
7
		(Revision	0.0.1)
8

  
9
		(ModificationStatus	NULL)
10

  
11
		(Status	Created)
12

  
13
		(ErrorStatus	0)
14

  
15
		(CreateInfo	
16

  
17
			(Time	05/24/11,17:09:11)
18

  
19
			(User	profs)
20

  
21
			(Path	_polytech_ge.transfo_1_2_sym)
22

  
23
		)
24

  
25
		(LastModifyInfo	
26

  
27
			(Time	10/07/10,15:10:00)
28

  
29
			(User	profs)
30

  
31
			(Path	_polytech_ge.transformateur_1_2_sym)
32

  
33
		)
34

  
35
	)
36

  
37
	(Views	
38

  
39
		(View	Symbol
40

  
41
			(Symbols	1
42

  
43
				(Symbol	sym_1
44

  
45
					(Symbol_Type	Normal)
46

  
47
					(Max_Size	0)
48

  
49
					(Checksum	000000006d8cb5ad)
50

  
51
					(RevisionInfoBlock	
52

  
53
						(Baselined	0)
54

  
55
						(Revision	0.0.1)
56

  
57
						(ModificationStatus	NULL)
58

  
59
						(Status	Created)
60

  
61
						(ErrorStatus	0)
62

  
63
						(CreateInfo	
64

  
65
							(Time	05/24/11,17:09:11)
66

  
67
							(User	profs)
68

  
69
							(Path	_polytech_ge.transfo_1_2_sym)
70

  
71
						)
72

  
73
					)
74

  
75
				)
76

  
77
			)
78

  
79
			(Checksum	000000001dc80412)
80

  
81
		)
82

  
83
		(View	Chips
84

  
85
			(Checksum	00000000548bd6f7)
86

  
87
			(Primitives	4
88

  
89
				(Primitive	transfo_1_2_sym_VCM
90

  
91
					(RevisionInfoBlock	
92

  
93
						(Baselined	0)
94

  
95
						(Revision	0.0.1)
96

  
97
						(ModificationStatus	NULL)
98

  
99
						(Status	Created)
100

  
101
						(ErrorStatus	0)
102

  
103
						(CreateInfo	
104

  
105
							(Time	05/24/11,17:09:11)
106

  
107
							(User	profs)
108

  
109
							(Path	_polytech_ge.transfo_1_2_sym)
110

  
111
						)
112

  
113
					)
114

  
115
					(LogicalPhysicalPartRelation	
116

  
117
						(LogicalPart	transfo_1_2_sym
118

  
119
							(PackType	transfo_1_2_sym_VCM)
120

  
121
						)
122

  
123
					)
124

  
125
					(Packages	1
126

  
127
						(FunctionGroups	1
128

  
129
							(FunctionGroup	1[1]
130

  
131
								(Linkages	
132

  
133
									(Linkage	Symbol
134

  
135
										(Name	sym_1)
136

  
137
									)
138

  
139
								)
140

  
141
							)
142

  
143
						)
144

  
145
						(Linkages	
146

  
147
							(DefaultFootPrint	
148

  
149
								(Name	transfo_vcm_2_24)
150

  
151
							)
152

  
153
						)
154

  
155
					)
156

  
157
				)
158

  
159
				(Primitive	transfo_1_2_sym_DS44060
160

  
161
					(RevisionInfoBlock	
162

  
163
						(Baselined	0)
164

  
165
						(Revision	0.0.1)
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167
						(ModificationStatus	NULL)
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169
						(Status	Created)
170

  
171
						(ErrorStatus	0)
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173
						(CreateInfo	
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175
							(Time	05/24/11,17:09:11)
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177
							(User	profs)
178

  
179
							(Path	_polytech_ge.transfo_1_2_sym)
180

  
181
						)
182

  
183
					)
184

  
185
					(LogicalPhysicalPartRelation	
186

  
187
						(LogicalPart	transfo_1_2_sym
188

  
189
							(PackType	transfo_1_2_sym_DS44060)
190

  
191
						)
192

  
193
					)
194

  
195
					(Packages	1
196

  
197
						(FunctionGroups	1
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199
							(FunctionGroup	1[1]
200

  
201
								(Linkages	
202

  
203
									(Linkage	Symbol
204

  
205
										(Name	sym_1)
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207
									)
208

  
209
								)
210

  
211
							)
212

  
213
						)
214

  
215
						(Linkages	
216

  
217
							(DefaultFootPrint	
218

  
219
								(Name	DS44060)
220

  
221
							)
222

  
223
						)
224

  
225
					)
226

  
227
				)
228

  
229
				(Primitive	transfo_1_2_sym_TR36_VA18
230

  
231
					(RevisionInfoBlock	
232

  
233
						(Baselined	0)
234

  
235
						(Revision	0.0.1)
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237
						(ModificationStatus	NULL)
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239
						(Status	Created)
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241
						(ErrorStatus	0)
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243
						(CreateInfo	
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245
							(Time	05/24/11,17:09:11)
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247
							(User	profs)
248

  
249
							(Path	_polytech_ge.transfo_1_2_sym)
250

  
251
						)
252

  
253
					)
254

  
255
					(LogicalPhysicalPartRelation	
256

  
257
						(LogicalPart	transfo_1_2_sym
258

  
259
							(PackType	transfo_1_2_sym_TR36_VA18)
260

  
261
						)
262

  
263
					)
264

  
265
					(Packages	1
266

  
267
						(FunctionGroups	1
268

  
269
							(FunctionGroup	1[1]
270

  
271
								(Linkages	
272

  
273
									(Linkage	Symbol
274

  
275
										(Name	sym_1)
276

  
277
									)
278

  
279
								)
280

  
281
							)
282

  
283
						)
284

  
285
						(Linkages	
286

  
287
							(DefaultFootPrint	
288

  
289
								(Name	TR18_36VA)
290

  
291
							)
292

  
293
						)
294

  
295
					)
296

  
297
				)
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299
				(Primitive	transfo_1_2_sym_SPK
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301
					(RevisionInfoBlock	
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303
						(Baselined	0)
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305
						(Revision	0.0.1)
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						(ModificationStatus	NULL)
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309
						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	05/24/11,17:09:11)
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317
							(User	profs)
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319
							(Path	_polytech_ge.transfo_1_2_sym)
320

  
321
						)
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323
					)
324

  
325
					(LogicalPhysicalPartRelation	
326

  
327
						(LogicalPart	transfo_1_2_sym
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329
							(PackType	transfo_1_2_sym_SPK)
330

  
331
						)
332

  
333
					)
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335
					(Packages	1
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337
						(FunctionGroups	1
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							(FunctionGroup	1[1]
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341
								(Linkages	
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343
									(Linkage	Symbol
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345
										(Name	sym_1)
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347
									)
348

  
349
								)
350

  
351
							)
352

  
353
						)
354

  
355
						(Linkages	
356

  
357
							(DefaultFootPrint	
358

  
359
								(Name	transfo_spk)
360

  
361
							)
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363
						)
364

  
365
					)
366

  
367
				)
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369
			)
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		)
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		(Checksum	000000001b720381)
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375
	)
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	(VersionInfoBlock	
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		(ToolName	PDV)
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		(Version	16.01-s021 (v16-1-53AR))
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		(License	Concept_HDL_expert)
384

  
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	)
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	(Checksum	000000001b440349)
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)
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trunk/librairies/polytech_ge/transfo_1_2_sym/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge/transfo_1_2_sym/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'TRANSFO_1_2_SYM_SPK';
3
  pin
4
    'S1P':
5
      PIN_NUMBER='(3)';
6
      PINUSE='UNSPEC';
7
      PIN_GROUP='2';
8
      NO_LOAD_CHECK='Both';
9
      NO_IO_CHECK='Both';
10
      NO_ASSERT_CHECK='TRUE';
11
      NO_DIR_CHECK='TRUE';
12
      ALLOW_CONNECT='TRUE';
13
    'S2P':
14
      PIN_NUMBER='(5)';
15
      PINUSE='UNSPEC';
16
      PIN_GROUP='3';
17
      NO_LOAD_CHECK='Both';
18
      NO_IO_CHECK='Both';
19
      NO_ASSERT_CHECK='TRUE';
20
      NO_DIR_CHECK='TRUE';
21
      ALLOW_CONNECT='TRUE';
22
    'S2N':
23
      PIN_NUMBER='(6)';
24
      PINUSE='UNSPEC';
25
      PIN_GROUP='3';
26
      NO_LOAD_CHECK='Both';
27
      NO_IO_CHECK='Both';
28
      NO_ASSERT_CHECK='TRUE';
29
      NO_DIR_CHECK='TRUE';
30
      ALLOW_CONNECT='TRUE';
31
    'P':
32
      PIN_NUMBER='(1)';
33
      PIN_TYPE='ANALOG';
34
      PIN_GROUP='1';
35
      NO_LOAD_CHECK='Both';
36
      NO_IO_CHECK='Both';
37
      NO_ASSERT_CHECK='TRUE';
38
      NO_DIR_CHECK='TRUE';
39
      ALLOW_CONNECT='TRUE';
40
    'N':
41
      PIN_NUMBER='(2)';
42
      PIN_TYPE='ANALOG';
43
      PIN_GROUP='1';
44
      NO_LOAD_CHECK='Both';
45
      NO_IO_CHECK='Both';
46
      NO_ASSERT_CHECK='TRUE';
47
      NO_DIR_CHECK='TRUE';
48
      ALLOW_CONNECT='TRUE';
49
    'S1N':
50
      PIN_NUMBER='(4)';
51
      PINUSE='UNSPEC';
52
      PIN_GROUP='2';
53
      NO_LOAD_CHECK='Both';
54
      NO_IO_CHECK='Both';
55
      NO_ASSERT_CHECK='TRUE';
56
      NO_DIR_CHECK='TRUE';
57
      ALLOW_CONNECT='TRUE';
58
  end_pin;
59
  body
60
    PART_NAME='transfo_1_2_sym';
61
    BODY_NAME='TRANSFO_1_2_SYM';
62
    JEDEC_TYPE='transfo_spk';
63
    PHYS_DES_PREFIX='T';
64
    CLASS='IC';
65
  end_body;
66
end_primitive;
67

  
68
primitive 'TRANSFO_1_2_SYM_VCM';
69
  pin
70
    'S1P':
71
      PIN_NUMBER='(3)';
72
      PINUSE='UNSPEC';
73
      NO_LOAD_CHECK='Both';
74
      NO_IO_CHECK='Both';
75
      NO_ASSERT_CHECK='TRUE';
76
      NO_DIR_CHECK='TRUE';
77
      ALLOW_CONNECT='TRUE';
78
    'S2P':
79
      PIN_NUMBER='(5)';
80
      PINUSE='UNSPEC';
81
      NO_LOAD_CHECK='Both';
82
      NO_IO_CHECK='Both';
83
      NO_ASSERT_CHECK='TRUE';
84
      NO_DIR_CHECK='TRUE';
85
      ALLOW_CONNECT='TRUE';
86
    'S2N':
87
      PIN_NUMBER='(6)';
88
      PINUSE='UNSPEC';
89
      NO_LOAD_CHECK='Both';
90
      NO_IO_CHECK='Both';
91
      NO_ASSERT_CHECK='TRUE';
92
      NO_DIR_CHECK='TRUE';
93
      ALLOW_CONNECT='TRUE';
94
    'P':
95
      PIN_NUMBER='(1)';
96
      PIN_TYPE='ANALOG';
97
      NO_LOAD_CHECK='Both';
98
      NO_IO_CHECK='Both';
99
      NO_ASSERT_CHECK='TRUE';
100
      NO_DIR_CHECK='TRUE';
101
      ALLOW_CONNECT='TRUE';
102
    'N':
103
      PIN_NUMBER='(2)';
104
      PIN_TYPE='ANALOG';
105
      NO_LOAD_CHECK='Both';
106
      NO_IO_CHECK='Both';
107
      NO_ASSERT_CHECK='TRUE';
108
      NO_DIR_CHECK='TRUE';
109
      ALLOW_CONNECT='TRUE';
110
    'S1N':
111
      PIN_NUMBER='(4)';
112
      PINUSE='UNSPEC';
113
      NO_LOAD_CHECK='Both';
114
      NO_IO_CHECK='Both';
115
      NO_ASSERT_CHECK='TRUE';
116
      NO_DIR_CHECK='TRUE';
117
      ALLOW_CONNECT='TRUE';
118
  end_pin;
119
  body
120
    PART_NAME='transfo_1_2_sym';
121
    BODY_NAME='TRANSFO_1_2_SYM';
122
    JEDEC_TYPE='transfo_vcm_2_24';
123
    PHYS_DES_PREFIX='U';
124
    CLASS='IC';
125
    NC_PINS='(7,8,9,10)';
126
  end_body;
127
end_primitive;
128

  
129
primitive 'TRANSFO_1_2_SYM_DS44060';
130
  pin
131
    'S1P':
132
      PIN_NUMBER='(7)';
133
      PINUSE='UNSPEC';
134
      NO_LOAD_CHECK='Both';
135
      NO_IO_CHECK='Both';
136
      NO_ASSERT_CHECK='TRUE';
137
      NO_DIR_CHECK='TRUE';
138
      ALLOW_CONNECT='TRUE';
139
    'S2P':
140
      PIN_NUMBER='(10)';
141
      PINUSE='UNSPEC';
142
      NO_LOAD_CHECK='Both';
143
      NO_IO_CHECK='Both';
144
      NO_ASSERT_CHECK='TRUE';
145
      NO_DIR_CHECK='TRUE';
146
      ALLOW_CONNECT='TRUE';
147
    'S2N':
148
      PIN_NUMBER='(9)';
149
      PINUSE='UNSPEC';
150
      NO_LOAD_CHECK='Both';
151
      NO_IO_CHECK='Both';
152
      NO_ASSERT_CHECK='TRUE';
153
      NO_DIR_CHECK='TRUE';
154
      ALLOW_CONNECT='TRUE';
155
    'P':
156
      PIN_NUMBER='(1)';
157
      PIN_TYPE='ANALOG';
158
      NO_LOAD_CHECK='Both';
159
      NO_IO_CHECK='Both';
160
      NO_ASSERT_CHECK='TRUE';
161
      NO_DIR_CHECK='TRUE';
162
      ALLOW_CONNECT='TRUE';
163
    'N':
164
      PIN_NUMBER='(5)';
165
      PIN_TYPE='ANALOG';
166
      NO_LOAD_CHECK='Both';
167
      NO_IO_CHECK='Both';
168
      NO_ASSERT_CHECK='TRUE';
169
      NO_DIR_CHECK='TRUE';
170
      ALLOW_CONNECT='TRUE';
171
    'S1N':
172
      PIN_NUMBER='(6)';
173
      PINUSE='UNSPEC';
174
      NO_LOAD_CHECK='Both';
175
      NO_IO_CHECK='Both';
176
      NO_ASSERT_CHECK='TRUE';
177
      NO_DIR_CHECK='TRUE';
178
      ALLOW_CONNECT='TRUE';
179
  end_pin;
180
  body
181
    PART_NAME='transfo_1_2_sym';
182
    BODY_NAME='TRANSFO_1_2_SYM';
183
    JEDEC_TYPE='DS44060';
184
    PHYS_DES_PREFIX='U';
185
    CLASS='IC';
186
  end_body;
187
end_primitive;
188

  
189
primitive 'TRANSFO_1_2_SYM_TR36_VA18';
190
  pin
191
    'S1P':
192
      PIN_NUMBER='(3)';
193
      PINUSE='UNSPEC';
194
      NO_LOAD_CHECK='Both';
195
      NO_IO_CHECK='Both';
196
      NO_ASSERT_CHECK='TRUE';
197
      NO_DIR_CHECK='TRUE';
198
      ALLOW_CONNECT='TRUE';
199
    'S2P':
200
      PIN_NUMBER='(5)';
201
      PINUSE='UNSPEC';
202
      NO_LOAD_CHECK='Both';
203
      NO_IO_CHECK='Both';
204
      NO_ASSERT_CHECK='TRUE';
205
      NO_DIR_CHECK='TRUE';
206
      ALLOW_CONNECT='TRUE';
207
    'S2N':
208
      PIN_NUMBER='(6)';
209
      PINUSE='UNSPEC';
210
      NO_LOAD_CHECK='Both';
211
      NO_IO_CHECK='Both';
212
      NO_ASSERT_CHECK='TRUE';
213
      NO_DIR_CHECK='TRUE';
214
      ALLOW_CONNECT='TRUE';
215
    'P':
216
      PIN_NUMBER='(1)';
217
      PIN_TYPE='ANALOG';
218
      NO_LOAD_CHECK='Both';
219
      NO_IO_CHECK='Both';
220
      NO_ASSERT_CHECK='TRUE';
221
      NO_DIR_CHECK='TRUE';
222
      ALLOW_CONNECT='TRUE';
223
    'N':
224
      PIN_NUMBER='(2)';
225
      PIN_TYPE='ANALOG';
226
      NO_LOAD_CHECK='Both';
227
      NO_IO_CHECK='Both';
228
      NO_ASSERT_CHECK='TRUE';
229
      NO_DIR_CHECK='TRUE';
230
      ALLOW_CONNECT='TRUE';
231
    'S1N':
232
      PIN_NUMBER='(4)';
233
      PINUSE='UNSPEC';
234
      NO_LOAD_CHECK='Both';
235
      NO_IO_CHECK='Both';
236
      NO_ASSERT_CHECK='TRUE';
237
      NO_DIR_CHECK='TRUE';
238
      ALLOW_CONNECT='TRUE';
239
  end_pin;
240
  body
241
    PART_NAME='transfo_1_2_sym';
242
    BODY_NAME='TRANSFO_1_2_SYM';
243
    JEDEC_TYPE='TR18_36VA';
244
    PHYS_DES_PREFIX='T';
245
    CLASS='IC';
246
  end_body;
247
end_primitive;
248

  
249
END.
trunk/librairies/polytech_ge/transfo_1_2_sym/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge/transfo_1_2_sym/sym_1/symbol.css
1
P "CDS_LMAN_SYM_OUTLINE" "-150,150,50,-200" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
2
L 50 150 50 -200 -1 0
3
L -150 150 50 150 -1 0
4
L -150 -200 50 -200 -1 0
5
L -150 -200 -150 150 -1 0
6
A 25 75 25 90 270 16
7
A 25 25 25 90 270 16
8
A -125 -25 25 270 450 16
9
A -125 75 25 270 450 16
10
A -125 25 25 270 450 16
11
A 25 -125 25 90 270 16
12
A 25 -75 25 90 270 16
13
A -125 -125 25 270 450 16
14
A -125 -75 25 270 450 16
15
P "$PATH" "?" 25 25 0 0 22 0 0 0 0 0 0 0 0
16
P "NEEDS_NO_SIZE" "TRUE" 25 75 0 0 22 0 0 0 0 0 0 0 0
17
P "PART_NAME" "transfo_1_2_sym" 0 0 0 0 22 0 0 0 0 0 0 0 0
18
P "PACK_TYPE" "SPK" -125 -225 0 0 22 0 0 0 0 0 1 0 0
19
P "$LOCATION" "?" -175 175 0 0 35 0 0 0 0 0 1 0 0
20
L 100 0 25 0 -1 0
21
C 100 0 "S1P" 122 0 0 1 22 0 L
22
L 100 -150 25 -150 -1 0
23
C 100 -150 "S2P" 122 -150 0 1 22 0 L
24
L 100 -50 25 -50 -1 0
25
C 100 -50 "S2N" 122 -50 0 1 22 0 L
26
L -200 -150 -125 -150 -1 0
27
C -200 -150 "P" -222 -150 0 1 22 0 R
28
L -200 100 -125 100 -1 0
29
C -200 100 "N" -222 100 0 1 22 0 R
30
L 100 100 25 100 -1 0
31
C 100 100 "S1N" 122 100 0 1 22 0 L
32

  
33

  
trunk/librairies/polytech_ge/transfo_1_2_sym/entity/master.tag
1
verilog.v
trunk/librairies/polytech_ge/transfo_1_2_sym/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on May 24, 2011  17:09:11
trunk/librairies/polytech_ge/transfo_1_2_sym/entity/verilog.v
1
// generated by newgenasym  Tue May 24 17:09:11 2011
2

  
3

  
4
module transfo_1_2_sym (n, p, s1n, s1p, s2n, s2p);
5
    inout n;
6
    inout p;
7
    inout s1n;
8
    inout s1p;
9
    inout s2n;
10
    inout s2p;
11

  
12

  
13
    initial
14
        begin
15
        end
16

  
17
endmodule
trunk/librairies/polytech_ge/transfo_1_2_sym/entity/vhdl.vhd
1
-- generated by newgenasym Tue May 24 17:09:11 2011
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity transfo_1_2_sym is
7
    port (    
8
	N:         INOUT  STD_LOGIC;    
9
	P:         INOUT  STD_LOGIC;    
10
	S1N:       INOUT  STD_LOGIC;    
11
	S1P:       INOUT  STD_LOGIC;    
12
	S2N:       INOUT  STD_LOGIC;    
13
	S2P:       INOUT  STD_LOGIC);
14
end transfo_1_2_sym;

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