Revision 245

View differences:

trunk/librairies/polytech_ge/inductor/chips/master.tag
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chips.prt
trunk/librairies/polytech_ge/inductor/chips/chips.prt
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FILE_TYPE=LIBRARY_PARTS ;
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TIME=' Compilation on Thu Sep 21 14:42:06 1989  ';
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PRIMITIVE 'INDUCTOR';
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 PIN
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  'A'<0>:
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   PIN_NUMBER='(1)';
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   PIN_GROUP='1';
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  'B'<0>:
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   PIN_NUMBER='(2)';
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   PIN_GROUP='1';
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 END_PIN;
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 BODY
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  PATH='23P';
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  DRAWING='ELEMENTCHIPS.LOGIC.1.1';
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  VER='1';
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  XY='(2750,2450)';
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  PHYS_DES_PREFIX='L';
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  DIR='ELEMENT.LIB';
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  ROT='0';
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  CLASS='DISCRETE';
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  PINCOUNT='2';
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  SIZE='1';
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  PART_NAME='INDUCTOR';
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  BODY_NAME='INDUCTOR';
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 END_BODY;
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END_PRIMITIVE;
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END.
trunk/librairies/polytech_ge/inductor/awb_dev/awb_dev.txt
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start DEVICE_INFO
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	MODEL_TYPE=2
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	SYMBOL_NAME=Inductor
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end DEVICE_INFO
trunk/librairies/polytech_ge/inductor/awb_dev/master.tag
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awb_dev.txt
trunk/librairies/polytech_ge/inductor/vlog_model/master.tag
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verilog.v
trunk/librairies/polytech_ge/inductor/vlog_model/verilog.v
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// generated by chdl_uprev Tue Nov 11 15:58:56 1997
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`timescale 1ns/100ps
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module inductor (a, b);
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    input [size-1:0] a;
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    inout [size-1:0] b;
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    IND  inst1[size-1:0] (.A(a),
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                               .B(b) );
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endmodule
trunk/librairies/polytech_ge/inductor/sym_1/master.tag
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symbol.css
trunk/librairies/polytech_ge/inductor/sym_1/symbol.css
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C -100 0 "A <SIZE-1..0>\NAC" -100 10 0 1 31 0 R
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P "SIZE" "1B" -80 113 0.00 0.00 32 0 0 0 0 0 0 0 2
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P "VALUE" "?" -80 73 0.00 0.00 32 0 0 0 0 0 1 0 0
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P "PATH" "?" -80 33 0.00 0.00 32 0 0 0 0 0 0 0 0
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P "IC" "UNDEF" -95 -88 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "TOL_ON_OFF" "ON" -95 -108 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "POSTOL" "LTOL%" -95 -128 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "NEGTOL" "LTOL%" -95 -148 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "DIST" "FLAT" -90 -168 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "CURRENT" "LMAX" -90 -188 0.00 0.00 16 0 0 0 0 0 0 0 0
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P "DIELECTRIC" "DSMAX" -90 -208 0.00 0.00 16 0 0 0 0 0 0 0 0
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L -85 10 -75 30 -1 0
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L -90 25 -70 15 -1 0
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L -75 10 -85 30 -1 0
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L -85 10 -75 10 -1 0
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L -90 15 -85 10 -1 0
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L -90 25 -90 15 -1 0
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L -85 30 -90 25 -1 0
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L -75 30 -85 30 -1 0
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L -70 25 -75 30 -1 0
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L -70 15 -70 25 -1 0
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L -75 10 -70 15 -1 0
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L 60 0 100 0 -1 0
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L -100 0 -60 0 -1 0
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A 45 1 15 356.13 183.78 0
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A -15 1 15 356.13 183.78 0
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A -45 1 15 356.13 183.78 0
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A 15 1 15 356.13 183.78 0
trunk/librairies/polytech_ge/inductor/sym_11/master.tag
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symbol.css
trunk/librairies/polytech_ge/inductor/sym_11/symbol.css
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C 0 -100 "B <SIZE-1..0>\NAC" -100 -200 0 0 41 0 L
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C 0 100 "A <SIZE-1..0>\NAC" -100 150 0 0 41 0 L
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L      0    100      0     67      -1 -122
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L      0    -65      0   -100      -1 -122
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A     0   -39    27 270.00 139.39 0
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A     0    40    28 225.00  90.00 0
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A     0     0    28 225.00 135.00 0
trunk/librairies/polytech_ge/inductor/sym_12/master.tag
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symbol.css
trunk/librairies/polytech_ge/inductor/sym_12/symbol.css
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C 100 0 "B <SIZE-1..0>\NAC" 150 0 0 0 41 0 L
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C -100 0 "A <SIZE-1..0>\NAC" -850 0 0 0 41 0 L
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P "SIZE" "1B" 0 50   0.00   0.00    41 0 0 0 0 0 1 0 0
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A   -38     1    28 310.61 180.00 0
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L   -100      0    -66      0      -1 -122
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L     66      0    100      0      -1 -122
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A    39     0    27   0.00 229.39 0
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A     0     0    28 315.00 225.00 0
trunk/librairies/polytech_ge/inductor/sym_13/master.tag
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symbol.css
trunk/librairies/polytech_ge/inductor/sym_13/symbol.css
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C 0 -100 "B <SIZE-1..0>\NAC" -100 -200 0 0 41 0 L
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C 0 100 "A <SIZE-1..0>\NAC" -100 150 0 0 41 0 L
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P "SIZE" "1B" 100 50   0.00   0.00    41 0 0 0 0 0 1 0 0
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L      0    -75      0   -100      -1 -122
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L      0     75     20     75      -1 -122
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L      0    100      0     75      -1 -122
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L      0    -75     20    -75      -1 -122
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L      0    -25     20    -25      -1 -122
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A    20   -50    25 270.00  90.00 0
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L      0     25     20     25      -1 -122
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A    20     0    25 270.00  90.00 0
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A    20    50    25 270.00  90.00 0
trunk/librairies/polytech_ge/inductor/entity/master.tag
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vhdl.vhd
trunk/librairies/polytech_ge/inductor/entity/pc.db
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-- pcdb file, Rev:1.0 written by VAN 1.02-p7 on Apr  7, 1997  14:45:01
trunk/librairies/polytech_ge/inductor/entity/verilog.v
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// generated by genview  Mon Apr  7 14:44:58 1997
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module inductor (a, b);
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    parameter    size = 1;
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    input  [size-1:0] a;
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    input  [size-1:0] b;
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    initial
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        begin
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        end
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endmodule
trunk/librairies/polytech_ge/inductor/entity/vhdl.vhd
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-- generated by genview  Mon Apr  7 14:44:59 1997
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity INDUCTOR is
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    generic (
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        size:positive:= 1
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            );
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    port (    
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	A:         IN     STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
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	B:         IN     STD_LOGIC_VECTOR (size-1 DOWNTO 0));
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end INDUCTOR;
trunk/librairies/polytech_ge/inductor/sym_14/master.tag
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symbol.css
trunk/librairies/polytech_ge/inductor/sym_14/symbol.css
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C 100 0 "B <SIZE-1..0>\NAC" 150 0 0 0 41 0 L
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C -100 0 "A <SIZE-1..0>\NAC" -850 0 0 0 41 0 L
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P "SIZE" "1B" 0 100   0.00   0.00    41 0 0 0 0 0 1 0 0
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L     75      0     75     20      -1 -122
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L     25      0     25     20      -1 -122
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A    50    20    25   0.00 180.00 0
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L    -25      0    -25     20      -1 -122
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A     0    20    25   0.00 180.00 0
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L    -75      0    -75     20      -1 -122
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A   -50    20    25   0.00 180.00 0
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L     75      0    100      0      -1 -122
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L   -100      0    -75      0      -1 -122

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