Revision 239

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trunk/librairies/polytech_ge/capacite/sym_1/symbol.css
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P "$LOCATION" "?" -75 25 0 0 41 0 0 0 0 0 1 0 72
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P "NEEDS_NO_SIZE" "TRUE" 0 0 0 0 22 0 0 0 0 0 0 0 0
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P "SYMMAP" "TRUE" 75 125 0 0 41 0 0 0 0 0 0 0 0
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P "$PATH" "?" 75 75 0 0 17 0 0 0 0 0 0 0 72
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P "REMOVE" "EXCLUDE" -375 -100 0 0 41 0 0 0 0 0 0 0 74
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P "PART_NAME" "CAPACITE" 0 0 0 0 22 0 0 0 0 0 0 0 0
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P "PACK_TYPE" "THRU_200_DECOUPLAGE" 0 25 0 0 14 0 0 0 0 0 1 0 0
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C 0 50 "A" -100 85 0 1 41 0 L
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X "$PN" "#" 0 100 90.00 0.00 40 0 0 0 0 0 0 0 32
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C 0 -50 "B" -100 -115 0 1 41 0 L
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X "$PN" "#" 0 0 90 0 40 0 0 0 0 0 0 0 32
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X "$PN" "#" 0 0 90.00 0.00 40 0 0 0 0 0 0 0 32
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L -50 -10 50 -10 -1 16
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L -50 10 50 10 -1 16
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L 0 10 0 50 -1 16
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C 0 50 "A" -100 85 0 1 41 0 L
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X "$PN" "#" 0 100 90 0 40 0 0 0 0 0 0 0 32
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L 0 -50 0 -10 -1 16
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P "VALUE" "10 UF" 25 -75 0.00 0.00 41 0 0 0 0 0 1 0 72
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P "PACK_TYPE" "THRU_200_DECOUPLAGE" 0 25 0.00 0.00 14 0 0 0 0 0 1 0 0
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P "PART_NAME" "CAPACITE" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "REMOVE" "EXCLUDE" -375 -100 0.00 0.00 41 0 0 0 0 0 0 0 74
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P "$PATH" "?" 75 75 0.00 0.00 17 0 0 0 0 0 0 0 72
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P "NEEDS_NO_SIZE" "TRUE" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "$LOCATION" "?" -75 25 0.00 0.00 41 0 0 0 0 0 1 0 72
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P "CDS_LMAN_SYM_OUTLINE" "-50,25,50,-25" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
trunk/librairies/polytech_ge/capacite/entity/master.tag
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vhdl.vhd
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verilog.v
trunk/librairies/polytech_ge/capacite/entity/verilog.v
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// generated by newgenasym  Mon Oct 18 15:35:41 2010
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// generated by newgenasym  Tue Nov 30 11:47:09 2010
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module capacite (a, b);
trunk/librairies/polytech_ge/capacite/entity/vhdl.vhd
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-- generated by newgenasym Mon Oct 18 15:35:41 2010
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-- generated by newgenasym Tue Nov 30 11:47:09 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity capacite is
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entity CAPACITE is
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    port (    
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	A:         INOUT  STD_LOGIC;    
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	B:         INOUT  STD_LOGIC);
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end capacite;
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end CAPACITE;

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