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-- generated by newgenasym Wed Oct 13 09:36:10 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity HE26 is
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    port (    
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	P1:        INOUT  STD_LOGIC;    
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	P10:       INOUT  STD_LOGIC;    
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	P11:       INOUT  STD_LOGIC;    
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	P12:       INOUT  STD_LOGIC;    
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	P13:       INOUT  STD_LOGIC;    
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	P14:       INOUT  STD_LOGIC;    
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	P15:       INOUT  STD_LOGIC;    
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	P16:       INOUT  STD_LOGIC;    
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	P17:       INOUT  STD_LOGIC;    
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	P18:       INOUT  STD_LOGIC;    
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	P19:       INOUT  STD_LOGIC;    
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	P2:        INOUT  STD_LOGIC;    
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	P20:       INOUT  STD_LOGIC;    
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	P21:       INOUT  STD_LOGIC;    
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	P22:       INOUT  STD_LOGIC;    
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	P23:       INOUT  STD_LOGIC;    
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	P24:       INOUT  STD_LOGIC;    
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	P25:       INOUT  STD_LOGIC;    
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	P26:       INOUT  STD_LOGIC;    
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	P3:        INOUT  STD_LOGIC;    
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	P4:        INOUT  STD_LOGIC;    
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	P5:        INOUT  STD_LOGIC;    
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	P6:        INOUT  STD_LOGIC;    
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	P7:        INOUT  STD_LOGIC;    
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	P8:        INOUT  STD_LOGIC;    
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	P9:        INOUT  STD_LOGIC);
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end HE26;