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-- generated by newgenasym Wed Nov 24 09:24:37 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity BP is
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    port (    
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	\1\:       INOUT  STD_LOGIC;    
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	\2\:       INOUT  STD_LOGIC);
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end BP;