Revision 222

View differences:

trunk/librairies/polytech_ge/bp/sym_1/symbol.css
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L -200 0 -50 0 -1 -2
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L -100 25 100 25 -1 16
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L -50 25 -50 50 -1 16
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L -50 50 50 50 -1 16
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L 50 50 50 25 -1 16
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L 200 0 50 0 -1 -2
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C -200 0 "1" -222 0 0 1 22 0 R
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C 200 0 "2" 222 0 0 1 22 0 L
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C 100 0 "2" 122 0 0 1 22 0 L
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C -100 0 "1" -122 0 0 1 22 0 R
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L -25 25 -25 50 -1 16
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L -25 50 25 50 -1 16
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L 25 50 25 25 -1 16
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L -50 25 50 25 -1 16
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L 100 0 50 0 -1 -2
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L -100 0 -50 0 -1 -2
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P "PART_NAME" "BP" -100 50 0.00 0.00 22 0 0 0 0 0 1 0 0
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P "$LOCATION" "?" -50 75 0.00 0.00 35 0 0 0 0 0 1 0 0
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P "$PATH" "?" 25 25 0.00 0.00 22 0 0 2 0 0 0 0 0
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0.00 0.00 28 0 0 0 0 0 0 0 0
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P "PACK_TYPE" "THRU" 0 50 0.00 0.00 11 0 0 0 0 0 1 0 0
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0.00 0.00 28 0 0 0 0 0 0 0 0
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P "$PATH" "?" 25 25 0.00 0.00 22 0 0 2 0 0 0 0 0
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P "$LOCATION" "?" -50 75 0.00 0.00 35 0 0 0 0 0 1 0 0
trunk/librairies/polytech_ge/bp/entity/verilog.v
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// generated by newgenasym  Fri Apr 11 10:51:33 2008
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// generated by newgenasym  Wed Nov 24 09:24:37 2010
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module bp (\1 , \2 );
trunk/librairies/polytech_ge/bp/entity/vhdl.vhd
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-- generated by newgenasym Fri Apr 11 10:51:33 2008
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-- generated by newgenasym Wed Nov 24 09:24:37 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity bp is
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entity BP is
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    port (    
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	\1\:       INOUT  STD_LOGIC;    
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	\2\:       INOUT  STD_LOGIC);
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end bp;
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end BP;
trunk/librairies/polytech_ge/quartz/sym_1/symbol.css
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C 100 0 "B\NAC" 122 0 0 1 22 0 L
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C -100 0 "A\NAC" -122 0 0 1 22 0 R
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C 75 0 "B\NAC" 97 0 0 1 22 0 L
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L -50 50 -50 -50 -1 16
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L 25 -50 25 50 -1 16
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L -25 -50 0 -50 -1 -2
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L -100 0 -50 0 -1 -2
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L -50 -50 -50 50 -1 16
6 5
L -25 50 -25 -50 -1 -2
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L 0 -50 0 50 -1 -2
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L -25 50 0 50 -1 -2
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L -100 0 -50 0 -1 -2
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L 75 0 25 0 -1 -2
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P "PACK_TYPE" "THRU" -25 -75 0.00 0.00 11 0 0 0 0 0 1 0 0
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P "$LOCATION" "?" -25 75 0.00 0.00 35 0 0 0 0 0 1 0 0
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L -25 50 25 50 -1 -2
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L -25 -50 25 -50 -1 -2
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L 25 -50 25 50 -1 -2
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L 50 50 50 -50 -1 16
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L 100 0 50 0 -1 -2
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P "PART_NAME" "QUARTZ" 25 125 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "$PATH" "?" 25 25 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "PACK_TYPE" "THRU" -25 -75 0.00 0.00 11 0 0 0 0 0 1 0 0
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P "$LOCATION" "?" -25 75 0.00 0.00 35 0 0 0 0 0 1 0 0
trunk/librairies/polytech_ge/quartz/entity/master.tag
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vhdl.vhd
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verilog.v
trunk/librairies/polytech_ge/quartz/entity/verilog.v
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// generated by newgenasym  Sun Mar 15 18:44:01 2009
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// generated by newgenasym  Wed Nov 24 08:57:48 2010
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module quartz (a, b);
trunk/librairies/polytech_ge/quartz/entity/vhdl.vhd
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-- generated by newgenasym Sun Mar 15 18:44:01 2009
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-- generated by newgenasym Wed Nov 24 08:57:48 2010
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library ieee;
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use     ieee.std_logic_1164.all;
trunk/librairies/polytech_ge/led/sym_1/symbol.css
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P "CDS_LMAN_SYM_OUTLINE" "-50,125,100,-50" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
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M -25 25 25 0 -1 0
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M -25 25 -25 -25 -1 0
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M -25 -25 25 0 -1 0
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M 25 -25 25 25 -1 0
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L 0 75 50 125 -1 16
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L 50 125 25 125 -1 16
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L 50 100 50 125 -1 16
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L 25 125 50 100 -1 16
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C 100 0 "K" 122 0 0 1 22 0 L
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C -100 0 "A" -122 0 0 1 22 0 R
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L -100 0 -25 0 -1 0
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M -25 25 -25 -25 -1 1
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M -25 25 25 0 -1 1
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M -25 -25 25 0 -1 1
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L 100 0 25 0 -1 16
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M 25 25 25 -25 -1 1
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L 50 50 100 100 -1 16
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L 100 75 100 100 -1 16
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L 100 100 75 100 -1 16
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L 75 100 100 75 -1 16
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L 100 75 100 100 -1 16
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L 50 50 100 100 -1 16
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A 0 0 50 0 360 16
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P "$LOCATION" "?" -100 50 0 0 35 0 0 0 0 0 1 0 0
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P "PACK_TYPE" "THRU_BROCHE07mm" -51 -72 0 0 11 0 0 0 0 0 1 0 0
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P "PART_NAME" "LED" 25 125 0 0 22 0 0 0 0 0 0 0 0
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0 0 22 0 0 0 0 0 0 0 0
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P "$PATH" "?" 25 25 0 0 22 0 0 0 0 0 0 0 0
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L 100 0 25 0 -1 16
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C 100 0 "K" 122 0 0 1 22 0 L
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L -75 0 -25 0 -1 0
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C -75 0 "A" -97 0 0 1 22 0 R
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25

  
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L 50 125 25 125 -1 16
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L 25 125 50 100 -1 16
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L 50 100 50 125 -1 16
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L 0 75 50 125 -1 16
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A 0 0 50 0.00 360.00 16
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P "$LOCATION" "?" -100 50 0.00 0.00 35 0 0 0 0 0 1 0 0
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P "$PATH" "?" 25 25 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "NEEDS_NO_SIZE" "TRUE" 25 75 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "PART_NAME" "LED" 25 125 0.00 0.00 22 0 0 0 0 0 0 0 0
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P "PACK_TYPE" "THRU_BROCHE07mm" -51 -72 0.00 0.00 11 0 0 0 0 0 1 0 0
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P "CDS_LMAN_SYM_OUTLINE" "-50,125,100,-50" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
trunk/librairies/polytech_ge/led/entity/master.tag
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vhdl.vhd
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verilog.v
trunk/librairies/polytech_ge/led/entity/verilog.v
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// generated by newgenasym  Fri Oct 01 16:04:24 2010
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// generated by newgenasym  Wed Nov 24 09:07:01 2010
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module led (a, k);
trunk/librairies/polytech_ge/led/entity/vhdl.vhd
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-- generated by newgenasym Fri Oct 01 16:04:24 2010
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-- generated by newgenasym Wed Nov 24 09:07:01 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity led is
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entity LED is
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    port (    
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	A:         INOUT  STD_LOGIC;    
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	K:         INOUT  STD_LOGIC);
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end led;
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end LED;

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