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psd-data / trunk / librairies / polytech_ge_beta / wm8731 / entity / verilog.v @ 217

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// generated by newgenasym  Fri Oct 22 15:52:52 2010
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module wm8731 (adcdat, adclrc, agnd, avdd, bclk, clkout, csb, dacdat,
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        daclrc, dbvdd, dcvdd, dgnd, hpgnd, hpvdd, lhpout, llinein,
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        lout, micbias, micin, mode, rhpout, rlinein, rout, sclk, sdin,
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        vmid, \xti/mclk , xto);
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    output adcdat;
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    input adclrc;
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    input agnd;
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    input avdd;
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    input bclk;
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    output clkout;
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    input csb;
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    input dacdat;
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    input daclrc;
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    input dbvdd;
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    input dcvdd;
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    input dgnd;
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    input hpgnd;
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    input hpvdd;
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    output lhpout;
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    input llinein;
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    output lout;
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    output micbias;
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    input micin;
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    input mode;
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    output rhpout;
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    input rlinein;
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    output rout;
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    input sclk;
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    input sdin;
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    output vmid;
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    input \xti/mclk ;
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    output xto;
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    initial
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        begin
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        end
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endmodule