Revision 214

View differences:

trunk/librairies/polytech_ge/bornier_5/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name A)
4
		(MSB )
5
		(LSB )
6
		(Type BIDIR)
7
		(Location Right)
8
		(InputLoadLow -0.01)
9
		(InputLoadHigh 0.01)
10
		(OutputLoadLow 1.0)
11
		(OutputLoadHigh -1.0)
12
		(CheckLoad Both)
13
		(CheckIO Both)
14
		(CheckDir 1)
15
		(CheckAssert 1)
16
		(CheckOutput 1)
17
		(UnknownLoading 0)
18
		(PinShape )
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name B)
25
		(MSB )
26
		(LSB )
27
		(Type BIDIR)
28
		(Location Right)
29
		(InputLoadLow -0.01)
30
		(InputLoadHigh 0.01)
31
		(OutputLoadLow 1.0)
32
		(OutputLoadHigh -1.0)
33
		(CheckLoad Both)
34
		(CheckIO Both)
35
		(CheckDir 1)
36
		(CheckAssert 1)
37
		(CheckOutput 1)
38
		(UnknownLoading 0)
39
		(PinShape )
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name C)
46
		(MSB )
47
		(LSB )
48
		(Type BIDIR)
49
		(Location Right)
50
		(InputLoadLow -0.01)
51
		(InputLoadHigh 0.01)
52
		(OutputLoadLow 1.0)
53
		(OutputLoadHigh -1.0)
54
		(CheckLoad Both)
55
		(CheckIO Both)
56
		(CheckDir 1)
57
		(CheckAssert 1)
58
		(CheckOutput 1)
59
		(UnknownLoading 0)
60
		(PinShape )
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65
	(Pin
66
		(Name D)
67
		(MSB )
68
		(LSB )
69
		(Type BIDIR)
70
		(Location Right)
71
		(InputLoadLow -0.01)
72
		(InputLoadHigh 0.01)
73
		(OutputLoadLow 1.0)
74
		(OutputLoadHigh -1.0)
75
		(CheckLoad Both)
76
		(CheckIO Both)
77
		(CheckDir 1)
78
		(CheckAssert 1)
79
		(CheckOutput 1)
80
		(UnknownLoading 0)
81
		(PinShape )
82
		(DIFF_PAIR_PINS_POS )
83
		(DIFF_PAIR_PINS_NEG )
84
	)
85

  
86
	(Pin
87
		(Name E)
88
		(MSB )
89
		(LSB )
90
		(Type BIDIR)
91
		(Location Right)
92
		(InputLoadLow -0.01)
93
		(InputLoadHigh 0.01)
94
		(OutputLoadLow 1.0)
95
		(OutputLoadHigh -1.0)
96
		(CheckLoad Both)
97
		(CheckIO Both)
98
		(CheckDir 1)
99
		(CheckAssert 1)
100
		(CheckOutput 1)
101
		(UnknownLoading 0)
102
		(PinShape )
103
		(DIFF_PAIR_PINS_POS )
104
		(DIFF_PAIR_PINS_NEG )
105
	)
106

  
107

  
108
)
trunk/librairies/polytech_ge/bornier_5/metadata/revision.dat
1
(Cell	bornier_5
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	(RevisionInfoBlock	
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		(Baselined	0)
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		(Revision	0.0.1)
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		(ModificationStatus	NULL)
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		(Status	Created)
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		(ErrorStatus	0)
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15
		(CreateInfo	
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17
			(Time	10/15/10,16:50:45)
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			(User	avercruy)
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			(Path	_polytech_ge.bornier_5)
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		(LastModifyInfo	
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			(Time	10/15/10,16:52:20)
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			(User	avercruy)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	10/15/10,16:50:45)
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							(User	avercruy)
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							(Path	_polytech_ge.bornier_5)
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	BORNIER_5
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							(PackType	BORNIER_5_THRU)
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					(Packages	1
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	SL5C)
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							)
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						)
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					)
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				)
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				(Primitive	BORNIER_5_MOLEX
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.1)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(CreateInfo	
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							(Time	10/15/10,16:50:48)
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							(User	avercruy)
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							(Path	_polytech_ge.bornier_5)
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						)
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	BORNIER_5
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									)
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							)
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						)
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	bornier_5_molex)
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							)
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					)
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				)
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		(Checksum	000000001e4103ee)
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	(VersionInfoBlock	
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		(ToolName	PDV)
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		(Version	16.01-s021 (v16-1-53AR))
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		(License	PCB_design_expert)
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	)
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	(Checksum	000000001bd003a9)
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)
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trunk/librairies/polytech_ge/bornier_5/entity/master.tag
1
vhdl.vhd
1
verilog.v
trunk/librairies/polytech_ge_beta/pcb/ssop28.log,1
1
(------------------------------------------------------------)
2
(                                                            )
3
(        Create Symbol of type PACKAGE                       )
4
(                                                            )
5
(        Drawing          : ssop28.dra                       )
6
(        Software Version : 16.1p001                         )
7
(        Date/Time        : Fri Oct 15 16:28:10 2010         )
8
(                                                            )
9
(------------------------------------------------------------)
10

  
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12

  
13
Create symbol started.
14
 
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Create symbol completed.
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trunk/librairies/polytech_ge_beta/mcp9701/metadata/pinlist.txt
1
(Pinlist
2
	(Pin
3
		(Name VDD)
4
		(MSB )
5
		(LSB )
6
		(Type INPUT)
7
		(Location Left)
8
		(InputLoadLow -0.01)
9
		(InputLoadHigh 0.01)
10
		(OutputLoadLow )
11
		(OutputLoadHigh )
12
		(CheckLoad Both)
13
		(CheckIO Both)
14
		(CheckDir 1)
15
		(CheckAssert 1)
16
		(CheckOutput 1)
17
		(UnknownLoading 0)
18
		(PinShape )
19
		(DIFF_PAIR_PINS_POS )
20
		(DIFF_PAIR_PINS_NEG )
21
	)
22

  
23
	(Pin
24
		(Name VOUT)
25
		(MSB )
26
		(LSB )
27
		(Type OUTPUT)
28
		(Location Right)
29
		(InputLoadLow )
30
		(InputLoadHigh )
31
		(OutputLoadLow 1.0)
32
		(OutputLoadHigh -1.0)
33
		(CheckLoad Both)
34
		(CheckIO Both)
35
		(CheckDir 1)
36
		(CheckAssert 1)
37
		(CheckOutput 1)
38
		(UnknownLoading 0)
39
		(PinShape )
40
		(DIFF_PAIR_PINS_POS )
41
		(DIFF_PAIR_PINS_NEG )
42
	)
43

  
44
	(Pin
45
		(Name GND)
46
		(MSB )
47
		(LSB )
48
		(Type GROUND)
49
		(Location Bottom)
50
		(InputLoadLow )
51
		(InputLoadHigh )
52
		(OutputLoadLow )
53
		(OutputLoadHigh )
54
		(CheckLoad Off)
55
		(CheckIO Off)
56
		(CheckDir 0)
57
		(CheckAssert 0)
58
		(CheckOutput 0)
59
		(UnknownLoading 0)
60
		(PinShape )
61
		(DIFF_PAIR_PINS_POS )
62
		(DIFF_PAIR_PINS_NEG )
63
	)
64

  
65

  
66
)
trunk/librairies/polytech_ge_beta/mcp9701/metadata/revision.dat
1
(Cell	mcp9701
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3
	(RevisionInfoBlock	
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5
		(Baselined	0)
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7
		(Revision	0.0.2)
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		(ModificationStatus	NULL)
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11
		(Status	Created)
12

  
13
		(ErrorStatus	0)
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15
		(CreateInfo	
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17
			(Time	10/15/10,13:51:03)
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			(User	avercruy)
20

  
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			(Path	_polytech_ge_beta.mcp9701)
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		)
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		(LastModifyInfo	
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			(Time	10/15/10,14:17:23)
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			(User	avercruy)
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			(Path	_polytech_ge_beta.mcp9701)
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	(Views	
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			(Primitives	1
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				(Primitive	MCP9701
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						(Revision	0.0.2)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	10/15/10,13:51:07)
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							(User	avercruy)
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							(Path	_polytech_ge_beta.mcp9701)
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						)
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					)
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	MCP9701
74

  
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							(PackType	MCP9701)
76

  
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						)
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					)
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					(Packages	1
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						(FunctionGroups	1
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							(FunctionGroup	1[1]
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								(Linkages	
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									(Linkage	Symbol
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	to92)
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			)
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				(Symbol	sym_1
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					(Max_Size	0)
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					(Checksum	000000001f586759)
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							(Time	10/15/10,14:17:22)
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trunk/librairies/polytech_ge_beta/mcp9701/chips/master.tag
1
chips.prt
trunk/librairies/polytech_ge_beta/mcp9701/chips/chips.prt
1
FILE_TYPE=LIBRARY_PARTS;
2
primitive 'MCP9701';
3
  pin
4
    'VDD':
5
      PIN_NUMBER='(3)';
6
      INPUT_LOAD='(-0.01,0.01)';
7
    'VOUT':
8
      PIN_NUMBER='(2)';
9
      OUTPUT_LOAD='(1.0,-1.0)';
10
    'GND':
11
      PIN_NUMBER='(1)';
12
      PINUSE='GROUND';
13
      NO_LOAD_CHECK='Both';
14
      NO_IO_CHECK='Both';
15
      NO_ASSERT_CHECK='TRUE';
16
      NO_DIR_CHECK='TRUE';
17
      ALLOW_CONNECT='TRUE';
18
  end_pin;
19
  body
20
    PART_NAME='MCP9701';
21
    BODY_NAME='MCP9701';
22
    JEDEC_TYPE='to92';
23
    PHYS_DES_PREFIX='U';
24
    CLASS='IC';
25
  end_body;
26
end_primitive;
27

  
28
END.
trunk/librairies/polytech_ge_beta/mcp9701/sym_1/symbol_css.lck
1
avercruy@2780
trunk/librairies/polytech_ge_beta/mcp9701/sym_1/symbol.css
1
C -200 0 "VDD" -225 0 0 1 29 0 R
2
X "PIN_TEXT" "VDD" -115 0 0.00 0.00 23 0 0 0 0 0 1 0 0
3
C 200 0 "VOUT" 225 0 0 1 29 0 L
4
X "PIN_TEXT" "VOUT" 115 0 0.00 0.00 23 0 0 2 0 0 1 0 0
5
C 0 -200 "GND" 0 -225 0 1 29 1 R
6
X "PIN_TEXT" "GND" 0 -115 90.00 0.00 23 0 0 0 0 0 1 0 0
7
L -125 -125 -125 125 -1 0
8
L 125 -125 -125 -125 -1 0
9
L -125 125 125 125 -1 0
10
L 125 -125 125 125 -1 0
11
L -200 0 -125 0 -1 0
12
L 0 -200 0 -125 -1 0
13
L 200 0 125 0 -1 0
14
T 0 83 0.00 0.00 29 0 0 1 0 7 0
15
mcp9701
16
P "CDS_LMAN_SYM_OUTLINE" "-125,125,125,-125" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
trunk/librairies/polytech_ge_beta/mcp9701/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct 15, 2010  14:17:24
trunk/librairies/polytech_ge_beta/mcp9701/entity/verilog.v
1
// generated by newgenasym  Fri Oct 15 14:25:40 2010
2

  
3

  
4
module mcp9701 (gnd, vdd, vout);
5
    input gnd;
6
    input vdd;
7
    output vout;
8

  
9

  
10
    initial
11
        begin
12
        end
13

  
14
endmodule
trunk/librairies/polytech_ge_beta/mcp9701/entity/vhdl.vhd
1
-- generated by newgenasym Fri Oct 15 14:25:40 2010
2

  
3
library ieee;
4
use     ieee.std_logic_1164.all;
5
use     work.all;
6
entity MCP9701 is
7
    port (    
8
	GND:       IN     STD_LOGIC;    
9
	VDD:       IN     STD_LOGIC;    
10
	VOUT:      OUT    STD_LOGIC);
11
end MCP9701;

Also available in: Unified diff