Revision 196 trunk/librairies/polytech_ge/nmos/entity/verilog.v

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verilog.v
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// generated by genview  Mon Apr 14 09:11:19 1997
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// generated by newgenasym  Fri Oct 15 16:48:53 2010
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module \nmos  (g, s, d);
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    inout  g;
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    inout  s;
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    inout  d;
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module \nmos  (d, g, s);
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    inout d;
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    inout g;
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    inout s;
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    initial

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