Revision 192

View differences:

trunk/librairies/polytech_ge/transformateur_2_2_sym/metadata/pinlist.txt
1 1
(Pinlist
2 2
	(Pin
3
		(Name P1)
3
		(Name SN2)
4 4
		(MSB )
5 5
		(LSB )
6 6
		(Type ANALOG)
......
42 42
	)
43 43

  
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	(Pin
45
		(Name SP2)
45
		(Name P1)
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		(MSB )
47 47
		(LSB )
48 48
		(Type ANALOG)
......
126 126
	)
127 127

  
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	(Pin
129
		(Name SN2)
129
		(Name SP2)
130 130
		(MSB )
131 131
		(LSB )
132 132
		(Type ANALOG)
trunk/librairies/polytech_ge/transformateur_2_2_sym/metadata/revision.dat
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		(Baselined	0)
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		(Revision	0.0.7)
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		(Revision	0.0.8)
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		(ModificationStatus	NULL)
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......
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					(Max_Size	0)
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					(Checksum	000000007fe8b067)
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					(Checksum	000000005420bebf)
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					(RevisionInfoBlock	
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......
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			)
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			(Checksum	000000001d8303ba)
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			(Checksum	000000001be103db)
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		)
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		(View	Chips
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			(Checksum	00000000ccbac907)
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			(Checksum	00000000f325c907)
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			(Primitives	2
88 88

  
......
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						(Baselined	0)
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						(Revision	0.0.3)
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						(Revision	0.0.4)
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						(ModificationStatus	NULL)
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......
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		)
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		(Checksum	000000001f710438)
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		(Checksum	000000001d0203db)
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	)
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......
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	)
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	(Checksum	000000001b5b034f)
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	(Checksum	000000001bb103a1)
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)
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trunk/librairies/polytech_ge/transformateur_2_2_sym/chips/chips.prt
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primitive 'TRANSFORMATEUR_2_2_SYM_TES_165';
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  pin
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    'P1':
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      PIN_NUMBER='(1)';
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    'SN2':
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      PIN_NUMBER='(4)';
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      PIN_TYPE='ANALOG';
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      PIN_GROUP='1';
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      PIN_GROUP='4';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'SP1':
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      PIN_NUMBER='(5)';
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      PIN_NUMBER='(1)';
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      PIN_TYPE='ANALOG';
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      PIN_GROUP='3';
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      NO_LOAD_CHECK='Both';
......
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'SP2':
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      PIN_NUMBER='(7)';
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    'P1':
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      PIN_NUMBER='(5)';
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      PIN_TYPE='ANALOG';
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      PIN_GROUP='4';
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      PIN_GROUP='1';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
115 115
    'N1':
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      PIN_NUMBER='(2)';
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      PIN_NUMBER='(6)';
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      PIN_TYPE='ANALOG';
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      PIN_GROUP='1';
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      NO_LOAD_CHECK='Both';
......
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
124 124
    'N2':
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      PIN_NUMBER='(4)';
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      PIN_NUMBER='(8)';
126 126
      PIN_TYPE='ANALOG';
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      PIN_GROUP='2';
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      NO_LOAD_CHECK='Both';
......
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'SN1':
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      PIN_NUMBER='(6)';
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      PIN_NUMBER='(2)';
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      PIN_TYPE='ANALOG';
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      PIN_GROUP='3';
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      NO_LOAD_CHECK='Both';
......
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'SN2':
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      PIN_NUMBER='(8)';
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    'SP2':
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      PIN_NUMBER='(3)';
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      PIN_TYPE='ANALOG';
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      PIN_GROUP='4';
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      NO_LOAD_CHECK='Both';
......
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'P2':
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      PIN_NUMBER='(3)';
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      PIN_NUMBER='(7)';
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      PIN_TYPE='ANALOG';
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      PIN_GROUP='2';
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      NO_LOAD_CHECK='Both';
trunk/librairies/polytech_ge/transformateur_2_2_sym/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct  8, 2010  16:42:36
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-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct 15, 2010  15:10:10
trunk/librairies/polytech_ge/transformateur_2_2_sym/entity/verilog.v
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// generated by newgenasym  Fri Oct 08 16:42:41 2010
1
// generated by newgenasym  Fri Oct 15 15:10:10 2010
2 2

  
3 3

  
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module transformateur_2_2_sym (n1, n2, p1, p2, sn1, sn2, sp1, sp2);
trunk/librairies/polytech_ge/transformateur_2_2_sym/entity/vhdl.vhd
1
-- generated by newgenasym Fri Oct 08 16:42:41 2010
1
-- generated by newgenasym Fri Oct 15 15:10:10 2010
2 2

  
3 3
library ieee;
4 4
use     ieee.std_logic_1164.all;
5 5
use     work.all;
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entity TRANSFORMATEUR_2_2_SYM is
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entity transformateur_2_2_sym is
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    port (    
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	N1:        INOUT  STD_LOGIC;    
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	N2:        INOUT  STD_LOGIC;    
......
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	SN2:       INOUT  STD_LOGIC;    
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	SP1:       INOUT  STD_LOGIC;    
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	SP2:       INOUT  STD_LOGIC);
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end TRANSFORMATEUR_2_2_SYM;
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end transformateur_2_2_sym;

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