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psd-data / trunk / librairies / polytech_ge_beta / pic18f4550 / entity / verilog.v @ 171

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// generated by newgenasym  Fri Oct 08 15:32:18 2010
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module pic18f4550 (\mclr/vpp/re3 , \osc1/clki , \osc2/clko/ra6 , \ra0/an0 , \ra1/an1 ,
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        \ra2/an2/vref-/cvref , \ra3/an3/vref+ , \ra4/t0cki/c1out/rcv ,
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        \ra5/an4/ss/hlvdin/c2out , \rb0/an12/int0/flt0/sdi/sda ,
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        \rb1/an10/int1/sck/scl , \rb2/an8/int2/vmo ,
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        \rb3/an9/ccp2/vpo , \rb4/an11/kbi0/csspp , \rb5/kbi1/pgm ,
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        \rb6/kbi2/pgc , \rb7/kbi3/pgd , \rc0/t1oso/t13cki ,
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        \rc1/t1osi/ccp2/uoe , \rc2/ccp1/p1a , \rc4/d-/vm , \rc5/d+/vp ,
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        \rc6/tx/ck , \rc7/rx/dt/sdo , \rd0/spp0 , \rd1/spp1 , \rd2/spp2 ,
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        \rd3/spp3 , \rd4/spp4 , \rd5/spp5/p1b , \rd6/spp6/p1c ,
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        \rd7/spp7/p1d , \re0/an5/ck1spp , \re1/an6/ck2spp ,
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        \re2/an7/oespp , vdd, vss, vusb);
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    input \mclr/vpp/re3 ;
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    input \osc1/clki ;
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    output \osc2/clko/ra6 ;
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    inout \ra0/an0 ;
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    inout \ra1/an1 ;
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    inout \ra2/an2/vref-/cvref ;
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    inout \ra3/an3/vref+ ;
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    inout \ra4/t0cki/c1out/rcv ;
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    inout \ra5/an4/ss/hlvdin/c2out ;
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    inout \rb0/an12/int0/flt0/sdi/sda ;
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    inout \rb1/an10/int1/sck/scl ;
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    inout \rb2/an8/int2/vmo ;
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    inout \rb3/an9/ccp2/vpo ;
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    inout \rb4/an11/kbi0/csspp ;
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    inout \rb5/kbi1/pgm ;
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    inout \rb6/kbi2/pgc ;
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    inout \rb7/kbi3/pgd ;
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    inout \rc0/t1oso/t13cki ;
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    inout \rc1/t1osi/ccp2/uoe ;
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    inout \rc2/ccp1/p1a ;
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    inout \rc4/d-/vm ;
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    inout \rc5/d+/vp ;
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    inout \rc6/tx/ck ;
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    inout \rc7/rx/dt/sdo ;
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    inout \rd0/spp0 ;
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    inout \rd1/spp1 ;
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    inout \rd2/spp2 ;
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    inout \rd3/spp3 ;
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    inout \rd4/spp4 ;
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    inout \rd5/spp5/p1b ;
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    inout \rd6/spp6/p1c ;
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    inout \rd7/spp7/p1d ;
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    inout \re0/an5/ck1spp ;
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    inout \re1/an6/ck2spp ;
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    inout \re2/an7/oespp ;
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    input [1:0] vdd;
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    input [1:0] vss;
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    inout vusb;
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    initial
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        begin
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        end
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endmodule