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psd-data / trunk / librairies / polytech_ge_beta / mc_7915 / entity / verilog.v @ 170

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// generated by newgenasym  Wed Oct 06 16:09:21 2010
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module mc_7915 (gnd1, in2, out3);
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    input gnd1;
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    input in2;
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    output out3;
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    initial
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        begin
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        end
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endmodule