Revision 169

View differences:

trunk/librairies/polytech_ge/capacite/metadata/pinlist.txt
15 15
		(CheckAssert 1)
16 16
		(CheckOutput 1)
17 17
		(UnknownLoading 0)
18
		(PinShape Line)
18
		(PinShape )
19 19
		(DIFF_PAIR_PINS_POS )
20 20
		(DIFF_PAIR_PINS_NEG )
21 21
	)
......
36 36
		(CheckAssert 1)
37 37
		(CheckOutput 1)
38 38
		(UnknownLoading 0)
39
		(PinShape Line)
39
		(PinShape )
40 40
		(DIFF_PAIR_PINS_POS )
41 41
		(DIFF_PAIR_PINS_NEG )
42 42
	)
trunk/librairies/polytech_ge/capacite/metadata/revision.dat
4 4

  
5 5
		(Baselined	0)
6 6

  
7
		(Revision	0.0.10)
7
		(Revision	0.0.11)
8 8

  
9 9
		(ModificationStatus	NULL)
10 10

  
......
24 24

  
25 25
		(LastModifyInfo	
26 26

  
27
			(Time	09/16/10,10:13:28)
27
			(Time	10/08/10,15:45:07)
28 28

  
29
			(User	profs)
29
			(User	oosman)
30 30

  
31 31
			(Path	_polytech_ge.capacite)
32 32

  
......
84 84

  
85 85
			(Checksum	000000009756c265)
86 86

  
87
			(Primitives	11
87
			(Primitives	12
88 88

  
89 89
				(Primitive	CAPACITE_THRU_CK05
90 90

  
......
856 856

  
857 857
				)
858 858

  
859
				(Primitive	CAPACITE_THRU_MKP
860

  
861
					(RevisionInfoBlock	
862

  
863
						(Baselined	0)
864

  
865
						(Revision	0.0.1)
866

  
867
						(ModificationStatus	NULL)
868

  
869
						(Status	Created)
870

  
871
						(ErrorStatus	0)
872

  
873
						(CreateInfo	
874

  
875
							(Time	10/08/10,15:44:48)
876

  
877
							(User	oosman)
878

  
879
							(Path	_polytech_ge.capacite)
880

  
881
						)
882

  
883
					)
884

  
885
					(LogicalPhysicalPartRelation	
886

  
887
						(LogicalPart	CAPACITE
888

  
889
							(PackType	CAPACITE_THRU_MKP)
890

  
891
						)
892

  
893
					)
894

  
895
					(Packages	1
896

  
897
						(FunctionGroups	1
898

  
899
							(FunctionGroup	1[1]
900

  
901
								(Linkages	
902

  
903
									(Linkage	Symbol
904

  
905
										(Name	sym_1)
906

  
907
									)
908

  
909
								)
910

  
911
							)
912

  
913
						)
914

  
915
						(Linkages	
916

  
917
							(DefaultFootPrint	
918

  
919
								(Name	mkp)
920

  
921
							)
922

  
923
						)
924

  
925
					)
926

  
927
				)
928

  
859 929
			)
860 930

  
861 931
		)
......
870 940

  
871 941
		(Version	16.01-s021 (v16-1-53AR))
872 942

  
873
		(License	PCB_librarian_expert)
943
		(License	PCB_design_expert)
874 944

  
875 945
	)
876 946

  
trunk/librairies/polytech_ge/capacite/chips/chips.prt
291 291
  end_body;
292 292
end_primitive;
293 293

  
294
primitive 'CAPACITE_THRU_MKP';
295
  pin
296
    'B':
297
      PIN_NUMBER='(2)';
298
      BIDIRECTIONAL='TRUE';
299
      PIN_GROUP='1';
300
      INPUT_LOAD='(-0.01,0.01)';
301
      OUTPUT_LOAD='(1.0,-1.0)';
302
    'A':
303
      PIN_NUMBER='(1)';
304
      BIDIRECTIONAL='TRUE';
305
      PIN_GROUP='1';
306
      INPUT_LOAD='(-0.01,0.01)';
307
      OUTPUT_LOAD='(1.0,-1.0)';
308
  end_pin;
309
  body
310
    PART_NAME='CAPACITE';
311
    ALLOW_CONNECT='TRUE';
312
    BODY_NAME='CAPACITE';
313
    PINCOUNT='2';
314
    SIZE='1';
315
    JEDEC_TYPE='mkp';
316
    PHYS_DES_PREFIX='C';
317
    CLASS='DISCRETE';
318
  end_body;
319
end_primitive;
320

  
294 321
END.
trunk/librairies/polytech_ge/capacite/entity/pc.db
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Sep 16, 2010  10:13:28
1
-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct  8, 2010  15:45:08
trunk/librairies/polytech_ge/capacite/entity/verilog.v
1
// generated by newgenasym  Thu Sep 16 10:13:28 2010
1
// generated by newgenasym  Fri Oct 08 15:45:07 2010
2 2

  
3 3

  
4 4
module capacite (a, b);
trunk/librairies/polytech_ge/capacite/entity/vhdl.vhd
1
-- generated by newgenasym Thu Sep 16 10:13:28 2010
1
-- generated by newgenasym Fri Oct 08 15:45:07 2010
2 2

  
3 3
library ieee;
4 4
use     ieee.std_logic_1164.all;

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