Revision 153

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trunk/librairies/polytech_ge_beta/pic18f4550/sym_2/symbol.css
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pic18f4550
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34

  
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P "$LOCATION" "?" -86 205 0.00 0.00 57 0 0 0 0 0 1 0 0
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P "CDS_LMAN_SYM_OUTLINE" "-75,200,525,-225" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
trunk/librairies/polytech_ge_beta/pic18f4550/entity/verilog.v
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// generated by newgenasym  Fri Sep 10 10:20:26 2010
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// generated by newgenasym  Wed Oct 06 16:30:03 2010
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module pic18f4550 (\mclr/vpp/re3 , \osc1/clki , \osc2/clko/ra6 , \ra0/an0 , \ra1/an1 ,
trunk/librairies/polytech_ge_beta/pic18f4550/entity/vhdl.vhd
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-- generated by newgenasym Fri Sep 10 10:20:26 2010
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-- generated by newgenasym Wed Oct 06 16:30:03 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity pic18f4550 is
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entity PIC18F4550 is
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    port (    
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	\mclr/vpp/re3\: IN     STD_LOGIC;    
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	\osc1/clki\: IN     STD_LOGIC;    
......
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	VDD:       IN     STD_LOGIC_VECTOR (1 DOWNTO 0);    
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	VSS:       IN     STD_LOGIC_VECTOR (1 DOWNTO 0);    
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	VUSB:      INOUT  STD_LOGIC);
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end pic18f4550;
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end PIC18F4550;

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