Revision 152

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trunk/librairies/polytech_ge_beta/80cpq150/metadata/pinlist.txt
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(Pinlist
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	(Pin
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		(Name ANODE1)
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		(MSB )
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		(LSB )
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		(Type ANALOG)
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		(Location Left)
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		(InputLoadLow )
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		(InputLoadHigh )
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		(OutputLoadLow )
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		(OutputLoadHigh )
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		(CheckLoad Off)
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		(CheckIO Off)
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		(CheckDir 0)
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		(CheckAssert 0)
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		(CheckOutput 0)
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		(UnknownLoading 0)
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		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
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		(DIFF_PAIR_PINS_NEG )
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	)
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	(Pin
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		(Name ANODE2)
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		(MSB )
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		(LSB )
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		(Type ANALOG)
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		(Location Left)
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		(InputLoadLow )
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		(InputLoadHigh )
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		(OutputLoadLow )
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		(OutputLoadHigh )
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		(CheckLoad Off)
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		(CheckIO Off)
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		(CheckDir 0)
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		(CheckAssert 0)
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		(CheckOutput 0)
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		(UnknownLoading 0)
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		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
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		(DIFF_PAIR_PINS_NEG )
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	)
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	(Pin
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		(Name CATHODE)
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		(MSB )
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		(LSB )
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		(Type ANALOG)
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		(Location Left)
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		(InputLoadLow )
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		(InputLoadHigh )
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		(OutputLoadLow )
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		(OutputLoadHigh )
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		(CheckLoad Off)
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		(CheckIO Off)
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		(CheckDir 0)
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		(CheckAssert 0)
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		(CheckOutput 0)
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		(UnknownLoading 0)
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		(PinShape Line)
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		(DIFF_PAIR_PINS_POS )
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		(DIFF_PAIR_PINS_NEG )
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	)
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)
trunk/librairies/polytech_ge_beta/80cpq150/metadata/master.tag
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revision.dat
trunk/librairies/polytech_ge_beta/80cpq150/metadata/revision.dat
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(Cell	80cpq150
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	(RevisionInfoBlock	
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		(Baselined	0)
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		(Revision	0.0.2)
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		(ModificationStatus	NULL)
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		(Status	Created)
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		(ErrorStatus	0)
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		(CreateInfo	
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			(Time	10/06/10,17:08:00)
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			(User	yabid)
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			(Path	_polytech_ge_beta.80cpq150)
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		)
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		(LastModifyInfo	
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			(Time	10/06/10,17:12:25)
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			(User	yabid)
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			(Path	_polytech_ge_beta.80cpq150)
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		)
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	)
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	(Views	
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		(View	Symbol
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			(Symbols	1
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				(Symbol	sym_1
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					(Symbol_Type	Normal)
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					(Max_Size	0)
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					(Checksum	000000009c2171d8)
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.1)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	10/06/10,17:11:53)
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							(User	yabid)
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							(Path	_polytech_ge_beta.80cpq150)
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						)
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					)
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				)
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			)
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			(Checksum	000000001bdd0384)
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		)
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		(View	Chips
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			(Checksum	00000000d6b7c9ed)
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			(Primitives	1
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				(Primitive	80CPQ150
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					(RevisionInfoBlock	
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						(Baselined	0)
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						(Revision	0.0.2)
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						(ModificationStatus	NULL)
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						(Status	Created)
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						(ErrorStatus	0)
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						(CreateInfo	
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							(Time	10/06/10,17:08:05)
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							(User	yabid)
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							(Path	_polytech_ge_beta.80cpq150)
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						)
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					)
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					(LogicalPhysicalPartRelation	
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						(LogicalPart	80CPQ150
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							(PackType	80CPQ150)
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						)
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					)
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					(Packages	1
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						(FunctionGroups	1
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							(FunctionGroup	1[1]
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								(Linkages	
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									(Linkage	Symbol
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										(Name	sym_1)
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									)
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								)
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							)
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						)
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						(Linkages	
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							(DefaultFootPrint	
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								(Name	to247ac)
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							)
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						)
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					)
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				)
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			)
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		)
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		(Checksum	000000001d0f03b5)
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	)
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	(VersionInfoBlock	
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		(ToolName	PDV)
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		(Version	16.01-s021 (v16-1-53AR))
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		(License	PCB_librarian_expert)
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	)
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	(Checksum	000000001c8403a6)
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)
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trunk/librairies/polytech_ge_beta/80cpq150/chips/master.tag
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chips.prt
trunk/librairies/polytech_ge_beta/80cpq150/chips/chips.prt
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FILE_TYPE=LIBRARY_PARTS;
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primitive '80CPQ150';
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  pin
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    'ANODE1':
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      PIN_NUMBER='(1)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'ANODE2':
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      PIN_NUMBER='(3)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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    'CATHODE':
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      PIN_NUMBER='(2)';
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      PIN_TYPE='ANALOG';
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      NO_LOAD_CHECK='Both';
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      NO_IO_CHECK='Both';
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      NO_ASSERT_CHECK='TRUE';
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      NO_DIR_CHECK='TRUE';
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      ALLOW_CONNECT='TRUE';
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  end_pin;
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  body
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    PART_NAME='80CPQ150';
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    BODY_NAME='80CPQ150';
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    JEDEC_TYPE='to247ac';
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    PHYS_DES_PREFIX='U';
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    CLASS='IC';
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  end_body;
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end_primitive;
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END.
trunk/librairies/polytech_ge_beta/80cpq150/sym_1/master.tag
1
symbol.css
trunk/librairies/polytech_ge_beta/80cpq150/sym_1/symbol.css
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C 0 150 "CATHODE" 250 125 0 1 29 0 R
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C -50 -100 "ANODE1" 0 -175 0 1 29 0 R
3
C 50 -100 "ANODE2" 200 -150 0 1 29 0 R
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L -100 -50 -100 75 -1 0
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L -100 -50 100 -50 -1 0
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L -100 75 100 75 -1 0
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L 100 75 100 -50 -1 0
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L -75 -25 -25 -25 -1 16
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L -75 -25 -50 25 -1 16
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L -50 25 -25 -25 -1 16
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L -50 50 -50 25 -1 16
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L -50 50 50 50 -1 16
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L 50 50 50 25 -1 16
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L 50 25 75 -25 -1 16
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L 25 -25 50 25 -1 16
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L 25 -25 75 -25 -1 16
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L -50 -100 -50 -25 -1 0
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L -25 25 -75 25 -1 16
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L 0 150 0 50 -1 0
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L 25 25 75 25 -1 16
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L 50 -100 50 -25 -1 0
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T 125 8 90.00 0.00 14 0 0 1 0 8 0
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80cpq150
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P "$LOCATION" "?" -109 84 0.00 0.00 57 0 0 0 0 0 1 0 0
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P "CDS_LMAN_SYM_OUTLINE" "-125,125,125,-125" 0 0 0.00 0.00 22 0 0 0 0 0 0 0 0
trunk/librairies/polytech_ge_beta/80cpq150/entity/master.tag
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verilog.v
trunk/librairies/polytech_ge_beta/80cpq150/entity/pc.db
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-- pcdb file, Rev:1.0 written by VAN 05.01-s01 on Oct  6, 2010  17:12:26
trunk/librairies/polytech_ge_beta/80cpq150/entity/verilog.v
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// generated by newgenasym  Wed Oct 06 17:17:03 2010
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module \80cpq150  (anode1, anode2, cathode);
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    inout anode1;
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    inout anode2;
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    inout cathode;
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    initial
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        begin
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        end
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endmodule
trunk/librairies/polytech_ge_beta/80cpq150/entity/vhdl.vhd
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-- generated by newgenasym Wed Oct 06 17:17:03 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity \80cpq150\ is
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    port (    
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	ANODE1:    INOUT  STD_LOGIC;    
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	ANODE2:    INOUT  STD_LOGIC;    
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	CATHODE:   INOUT  STD_LOGIC);
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end \80cpq150\;

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