Revision 149 trunk/librairies/polytech_ge_beta/relais_1c_1p/entity/vhdl.vhd

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vhdl.vhd
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-- generated by newgenasym Wed Sep 29 14:17:48 2010
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-- generated by newgenasym Wed Oct 06 15:51:10 2010
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library ieee;
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use     ieee.std_logic_1164.all;
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use     work.all;
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entity relais_1c_1p is
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entity RELAIS_1C_1P is
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    port (    
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	\1\:       INOUT  STD_LOGIC;    
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	\3\:       INOUT  STD_LOGIC;    
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	\5\:       INOUT  STD_LOGIC;    
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	\7\:       INOUT  STD_LOGIC);
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end relais_1c_1p;
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end RELAIS_1C_1P;

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